News Article

Intel Scores Another InGaAs-on-silicon Goal

The world-leading silicon chip maker eyes the potential of III-V materials to cut transistor power consumption.

By Michael Hatcher in Washington, DC
Intel has made the first enhancement-mode InGaAs quantum wells to be fabricated on a silicon substrate.

The enhancement-mode transistor advances the chip giant s existing compounds-on-silicon efforts closer to practical deployment.

Previously Intel had only made depletion mode, or normally-on, InGaAs-on-silicon transistors, through which current flows continuously until a switching voltage is applied. For power efficiency reasons, Intel has sought to develop an enhancement-mode, normally-off, device instead.

The development, which hinges on a metamorphic buffer zone that effectively "filters out" defects, could pave the way to future integration of III-V materials in CMOS wafer processing.

Combining high-performance GaAs with the process advantages of a silicon platform has long been seen as a way to scale to faster, more efficient logic devices.

However, in reality, the large lattice mismatch between the materials, on top of their differing polarities and thermal properties, results in huge problems with defects, dislocations and phase boundaries.

To get around that, Mantu Hudait and colleagues deposited a buffer comprising a thick GaAs layer, and two thinner layers of InAlAs, onto (100) orientation silicon.

Presenting the results to a packed room at the International Electron Devices Meeting in Washington, DC, Hudait said that the metamorphic buffer “filtered out" dislocations caused by the various material mismatches, leaving a high-quality InGaAs channel region.

Having done that with a 3.2 micron buffer, the Intel team set about reducing the buffer thickness as much as possible, without impacting the overall material quality.

They reduced the layer to a more practical 1.3 microns, without noticing any adverse effects.

X-ray measurements showed a defect-free quantum well stack, results that were backed up by a consistent quantum well mobility when structures grown on different host materials were studied.

Using an 80nm gate, Hudait and colleagues found that the quantum well transistor operated in enhancement-mode, with a threshold voltage of 0.11V.

Intel says that the material combination could potentially cut power dissipation by a factor of ten, or double the speed, of a comparable silicon transistor.

Though any commercial introduction of the technology remains distant, some in the semiconductor industry now believe that III-V materials have a real chance of CMOS integration - perhaps by 2015.

Back in 2001, Motorola announced that it had developed a GaAs-on-silicon approach suitable for RF applications (see related story). However, it then proved impossible to reduce defect densities to a suitable level for the technology to succeed.

Author
Michael Hatcher is editor of Compound Semiconductor magazine and compoundsemiconductor.net.

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