News Article

Wafer-scale Approach Simplifies Hermetic Packaging

Hermetic wafer-level packaging can cut the cost and weight of III-V MMIC protection and offer a route to combining different types of chip in a single compact module, say Patty Chang-Chien, Xianglin Zeng, Yun Chung and Jeff Yang from Northrop Grumman Space Technology.

Tough environments are the norm for RF electronics employed in space and military applications. Moisture, mechanical vibrations and temperature extremes can all degrade performance, so chips are protected by packages featuring airtight hermetic sealing that improve device lifetime and reliability.

Traditionally, the process used for making sealed packages begins with semiconductor chip fabrication, which includes a passivation step to provide minor protection. These "bare" MMICs are then packaged in ball grid arrays – an assembly of pins for parallel soldering to devices – before being placed in integrated microwave assemblies (IMAs) for hermetic sealing at the submodule level. Sealing is carried out on each unit after several MMICs have been mounted on a board. Electrical connections to the board are then made by wire bonding, or use of the ball grid array, and the device is finally subjected to a series of pre- and post-seal tests to assess electrical, mechanical and hermeticity properties.

Unfortunately, this approach suffers from a major weakness. If any device does not meet its specification, or if any IMA fails a test, then the IMA has to be broken apart and any offending parts replaced. Consequently, this process for hermetic packaging is costly, labor intensive and time consuming.

However, substantial cost savings are possible by employing the hermetic seal at the wafer level instead of at the IMA stage. Hermeticity is then restricted to the sensitive, high-performance microelectronics that are sealed at the wafer level in die form using batch fabrication. This is cheaper, because there are fewer assembly steps and tests, and it has the added benefit of compatibility with non-hermetic IMA materials that are cheaper, lighter and easier to use. Failed chips are also easier to deal with because bad parts can be replaced and several steps associated with conventional packages are avoided, such as re-sealing and testing of the IMA module. The removal of seam sealing also simplifies system diagnostics, which cuts module-level test times and costs.

The bulky, heavy packages and metal housings used in conventional modules to meet the IMA s hermeticity requirement can also be eliminated with wafer-level packaging (WLP). This is a major plus point for space applications as it cuts the system s weight and launch costs – an IC-based hermetic WLP transceiver can weigh just 100th of an equivalent packaged with ball grid arrays.

WLP techniques are already being employed in silicon-based systems, such as the accelerometers in automobile air-bags. At Northrop Grumman Space Technology, Redondo Beach, CA, we have extended this technology to high-performance, high-frequency RF MMICs made from III-Vs. This process features new wafer-level bonding techniques.

We have focused our process development around four key issues: process and device compatibility, hermeticity, package reliability and cost.

Heat can degrade MMICs and modules, so this must be avoided during packaging. High-temperature wafer bonding leads to thermal stresses between dissimilar materials and if MBE-grown III-V circuits get too hot, thermal diffusion between epilayers compromises device reliability. To prevent these problems, we have developed a process that combines the low-temperature solder bonding with the thermodynamic stability of metal alloy bonding. Rugged topographies are not a problem and high bonding and interconnect yields are possible at 180 °C. This technology is also versatile – it can be used for standard assembly processes, such as solder bumping and the bonding of multiple wafer stacks – which makes it suitable for packaging MMICs and multiwafer heterogeneous integration.

High-quality hermetic seals are essential for MMIC packaging because they enclose devices in an environment that is free from moisture and undesirable organic materials. This is particularly important for packages immersed in liquid or high-humidity environments, which often fail due to moisture penetration and condensation on the active regions of devices. Out-gasing can jeopardize cavity hermeticity, ruling out the use of certain polymers and materials. Oxygen can also degrade MMIC performance, although this can be avoided by filling the cavity with an inert gas, such as nitrogen.

Reliable packaging is essential for long-term performance, so sealing must be chemically and physically stable over the product s lifetime. A mismatch between the material properties of the packaging and device – which come together during wafer bonding – can lead to cracking, deformation and an unstable MMIC with noisy performance. To combat this, the packaging must employ an appropriate design that is compatible with low-temperature processes.

Cost is obviously a key issue. This can be driven down with a high-volume batch fabrication and the use of mature packaging methods that only require a few processing steps. Although the WLP process is expensive at the MMIC/device level, this is outweighed by the savings made at the submodule or module level, where time-consuming assembly and tests dominate the cost.

Our WLP process, which is suitable for batch fabrication and single-module production, starts with substrates and cover wafers (figure 1). Both are processed with standard MMIC fabrication techniques, before matching metallic rings are added using intracavity interconnection (ICIC) layers. A bonding layer is applied to the top of one of the wafer s ICIC layers, before backside processes produce ground vias to complete MMIC fabrication. Low-temperature bonding follows, resulting in circuitry that is encapsulated in sealed cavities between the wafer surfaces and bonding rings. These chips are then accessed by through-wafer vias formed by our MMIC backside fabrication processes. Vertical rather than lateral RF feed-through approaches are adopted to minimize the parasitic feed-through losses at high frequencies.

To demonstrate our technology s capability, we have also built MMICs operating from the UHF-band to the W-band. Wafer-level testing demonstrates the complete compatibility of our technology with existing III-V production processes and its suitability for high-frequency, high-performance RF MMIC packaging (figure 3).

Hermetic sealing of individual MMICs can deliver submodule or IMA assembly cost savings, but further reductions and performance enhancements are possible by combining multiple chips/functions within a single package. This can be delivered by combining multiple chips with the same III-V fabrication technology into a multifunctional chip; or by uniting different semiconductor technologies in a vertical stack; or by building more complicated assemblies that draw on both of these themes.

All of these approaches can lead to three-dimensional heterogeneous ICs that benefit from the interplay of different devices. For example, high-performance, low-noise InP amplifiers can be built into circuits also featuring GaAs or GaN power amplifiers without any performance degradation. This involves a relatively simple, low-cost process, thanks to shared packaging steps. In fact, it is possible to extend this heterogeneous integration capability by uniting silicon-based digital circuits with RF MMICs using the same processes.

This type of wafer-level packaged IC can deliver significant cost and system-level performance enhancements over today s state-of-the-art packaging, which relies on multilayer, densely packed ball grid array modules. The WLP process can bring different circuits into close proximity without the need for additional board material and MMIC pick-and-place assembly. In addition, fewer components and component-to-component interfaces and interconnections are required, such as wire bonds. This ultimately cuts ohmic loss and wire-induced parasitics in the ICs, which is a significant benefit for high-frequency circuits.

To show this heterogeneous integration capability, we have built an integrated antenna RF front-end module. The assembly consists of a GaAs HEMT, a Q-band power amplifier, a 3-bit phase shifter and ICICs that provide RF and DC routings. A ring slot antenna is integrated on the outside of the package and is connected to the circuitry by a through-wafer via on the cover wafer and an ICIC within the cavity. Tests confirmed the expected performance levels and were used to construct a four-element linear electronically steerable array (figure 4).

A variety of WLP circuits have been tested under criteria laid out by the US military. They passed all of the tests, which are designed to assess mechanical, thermal and environmental integrity and hermeticity (see box "Military testing" for details).

To date, we have demonstrated the functionality and compatibility of our WLP technology with many III-V technologies, including GaAs and InP HEMT and HBTs, and antimony-based HEMTs. We are now extending our work to cover silicon and GaN circuitries. Currently, multiple projects are underway to develop our WLP technology; to investigate multilayer, multisemiconductor technology module construction using this WLP assembly technology; and to incorporate more functional blocks into compact integrated RF front-end modules.

Our current WLP processes produce devices with a DC functional yield exceeding 99%, while the RF yield is typically limited by the particular semiconductor technology employed for packaging within the cavity. Our packages also have excellent mechanical and thermal robustness, according to various military tests, and we are now conducting long-term device/package reliability tests to qualify the technology for military and space use.

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