Patent flurry reveals GaN-on-silicon schemes
Three patent filings published in January 2008 demonstrate how to tackle the weighty problem of depositing GaN on silicon substrates "“ including one that highlights a “universal” method for III-V growth on silicon.
The US patent office publications all take novel approaches to buffering the 17 percent lattice mismatch between GaN and silicon.
Qinetiq claims that its technique (see related links) could broaden the benefits of lower-cost silicon substrates to more than just LED manufacture. The UK-based company proposes group IIIB lanthanide nitrides to form intermediate layers that will reduce the number of defects seen in III-V materials grown on silicon.
“We have found that the physical properties and crystal structures of the Group IIIB nitrides make them particularly suitable for providing graded buffer structures on silicon that allow high-quality target material layers to be deposited,” Qinetiq s researchers write.
The patent says that Qinetiq specifically grew a LaScN alloy using MBE between 700°C and 900°C, after depositing a monolayer of lanthanum metal on a 111 silicon surface.
A compositionally graded buffer layer was produced by varying the amounts of scandium and lanthanum in the growth gas mixture, changing the proportions of the Group IIIB elements with depth in the buffer layer. This is pivotal to the lanthanide approach, as it allows Qinetiq to create a lattice with highly suitable properties to support subsequent compound semiconductor material growth.
“Within the Group IIIB nitrides there is sufficient diversity of lattice parameters within their respective cubic structures to facilitate the production of a universal , silicon-based substrate for epitaxial growth,” the company says.
Korea developments
Two patent filings from Samsung are more closely focused on making LED epiwafers. The Korean corporation has been granted one patent based on the kind of AlN buffer that has previously been used to integrate GaN and silicon.
Researchers from Samsung Electro-Mechanics deposit the materials at particularly high temperatures "“ ranging between 1050 and 1200°C, in comparison to conventional methods that use temperatures of 500 to 700°C.
After the AlN buffer has been grown, two GaN layers follow, the first of which uses a 6000-fold excess of ammonia to trimethylgallium at pressures ranging between 300 and 760 torr. The excess of ammonia in the second GaN layer is 3000-fold or less and the pressure preferably between 10 and 50 torr that achieves two-dimensional growth.
The lower pressures used in the GaN nitride deposition steps encourage sideways, rather than vertical, crystal growth. According to Samsung, this lateral growth “remarkably improves surface roughness of the GaN layer”.
As well as the AlN buffer, the first GaN layer helps to absorb stress from lattice mismatch or differences in thermal expansion coefficient. This then allows Samsung to produce crack-free GaN with defect densities of 108 or less in the upper layer.
The second publication, a new application from Samsung Electronics Co., Ltd., again uses unusual materials to push GaN-on-silicon growth forward. In this case a ZnO intermediate layer helps to form the basis for the LED structure.
ZnO acts as a buffer between possible base substrate materials, which include silicon, and the GaN that is subsequently deposited using a lateral growth method. Samsung Electronics filing uses ion bombardment to turn strips of crystalline ZnO material into its amorphous form.
The amorphous stripes effectively behave as masks, so that when GaN is grown on top, it initially forms on the crystalline ZnO strips and then, again, expands laterally.
Using this approach the patent claims to make GaN wafers ready for LED epitaxy with less than 108 defects/cm2, and potentially as little as 104 defects/cm2.
