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Avago Shrinks Its Chip Footprint

Surface mount processes that populate printed circuit boards with passives can now add active die too, thanks to Avago's WaferCap technology. This ultimately opens up a path to low-cost amplification for cable TV, base stations and instrumentation, says the company's Jim Roland.

There are numerous uses of wireless connectivity. It s employed for simple tasks, such as opening a garage door, through to highly complex military applications that demand ultra-small radio sensors.

In many cases, the manufacturers of these wireless products are looking for RF components that meet three criteria: a very thin profile; the ability to support high data rates; and competitive pricing, which is a big factor for products that are launched in consumer markets.

At Avago Technologies Wireless Semiconductor Division, which is headquartered in San Jose, CA, we fulfill all of these requirements with our innovative WaferCap packaging technology.

WaferCap is a process that joins a 6 inch GaAs wafer with processed transistors to a bare wafer of the same dimensions with a polymer gasket seal. This encloses the perimeter of the die to create an air-cavity wafer-scale package, which differentiates it from the majority of chip-scale packaging technologies that are currently in use. The bonded wafers are then cut up into thousands of individual, robust packages that have the potential to operate at up to 100 GHz, thanks to the low dielectric constant of the air cavity above the active region.

The production of a typical RF package involves wafer manufacture and die packaging at separate locations, using different equipment and process skills. But with our approach we can greatly simplify the supply chain, because the same site is used for wafer fabrication, wafer bonding, via and pad formation, test and dicing.

Our WaferCap package is intentionally the same size as the widely used 0402 component – 1 mm × 0.5 mm × 0.25 mm. This is compatible with standard tape and reel sizes, and means that printed circuit boards can be populated with our die using inexpensive surface mount technology that is normally restricted to passive components. Both active and passive components can be attached during the same process, leading to time and cost savings. The WaferCap format shrinks the RF device s footprint on a printed circuit board by up to 50% compared with a standard package.

This approach compares favorably to that used for the more common bare die, which have a more complicated supply chain. For bare die, after they are attached with conductive epoxy and wire-bonded, an additional polymer coating is needed to protect the exposed wire bonds and the die s active surfaces.

With the approach that we advocate, surface mount attach costs are minimized through screen printing with lead-free solder paste, helping parts to self-align on the printed circuit board. Passives are added, along with other elements with solderable pads, before the entire assembly is transferred to an oven to complete the soldering process.

The solderable pads for WaferCap are designed in the same way as the pads for a typical passive component. They are terminated with a solderable metallic layer, typically copper or nickel, and coating this layer or chemically treating it prevents oxidation. Neither approach inhibits the solder contact.

Another consideration for the WaferCap solderable pads is to protect the underlying metal, which is used to make electrical contact through backside vias, from the solder environment. This is done by inserting a conductive barrier layer between the solderable metal and underlying pad metal.

Soldered parts that have been attached to the pads in this manner have passed several qualification tests, including multiple reflow and shear, drop, cycle bending, vibration and thermal cycle.

RF performance advantages

Our WaferCap design provides short lead lengths, minimal inductance with low variability and RF transitions with minimal parasitic loss, thanks to routing of input and output signals along the backside of the device wafer through via holes. This is a massive improvement over conventional plastic packages, which have higher parasitic losses that degrade performance. Their inferiority results from the high-dielectric-loss carbon polymer that encapsulates bond wires and active circuits. Our approach also delivers a greater consistency of the lead design, which removes the need to tune wire bonds.

Device modeling suggests that our devices can form amplifiers operating in the 17–33 GHz range (Microwave Journal August 2008). These simulations show that our chips are capable of operating well beyond 50 GHz and we believe that they have the potential to stretch to 100 GHz.

We have investigated several applications that can derive the biggest benefit from the unique properties of WaferCap technology. Three different amplifier designs have been developed – a 1–12 GHz 50 Ω gain block, a 0.5–6 GHz bypass low-noise amplifier (LNA) and a 1–6 GHz low-voltage LNA. We have recently detailed each of these designs at the European Microwave Conference, which was held in Amsterdam, the Netherlands, on October 27–31.

These three amplifiers could serve many commercial wireless applications in the 0.5–12 GHz range. However, we believe that they will also prove their worth in other markets. They could be used to provide broadband amplification to signals transmitted through coaxial cable for cable TV, or deliver amplification in base stations and instrumentation.

We have started by incorporating our enhancement-mode PHEMT technology into WaferCap products. This creates high dynamic range, ultra-low-noise integrated circuits with high gain, which can operate from a single positive DC supply.

Our next step will be to design additional products into the 0402 package format. Customers are currently evaluating some of these parts (see table 1 for details), which could form the building blocks of circuits targeting specific applications.
Further down the road we will be launching a two-pronged process development program. One aim is to extend our WaferCap technology to include other types of transistor, such as enhancement-mode and depletion-mode HEMTs. We are also aiming to extend it to other standard package sizes. Going smaller will cut costs, while increasing size promises more integration and greater performance. We re planning to release products based on this development in 2009, which will allow our customers to enjoy more benefits from this technology.

Further reading

An interactive video presentation describing Avago s WaferCap technology can be seen at More information is available at


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