News Article

HRL Marries InP And CMOS Wafers

At IEDM, the research lab demonstrates that CMOS performance does not have to be compromised by heterogeneous bonding to InP DHBT wafers.

Scientists at HRL Laboratories in Malibu, CA, have combined InP and CMOS in a breakthrough that could allow rapid adoption of more advanced integrated technology.

The researchers, who are presenting their work at the IEEE Electron Devices Meeting in San Francisco, California, married 300 GHz InP double HBTs (DHBTs) with 130 nm RF-CMOS technology at the wafer level.

This approach allows the superior performance of InP transistors to be united with a silicon manufacturing technology that can produce ICs exploiting over a billion transistors in high volume.

The technology developed by HRL can join 3-inch and 100 mm InP DHBT wafers to 200 mm or 300 mm CMOS wafers created by IBM s CMRF8SF process. The InP transistors featured 0.25 µm by 4 µm emitters.

“No electrical impact to the CMOS devices has yet been observed, and the InP DHBTs suffer minimal performance degradation," write James Li and his co-authors in their paper.

Li and colleagues say that this is the first demonstration of un-perturbed CMOS performance after heterogeneous integration with an InP HBT.

The DHBT s cut-off frequency (fT) is above 300  GHz, but the maximum oscillation frequency (fMAX) is below 150 GHz, a value that the researchers describe as “modest".

According to them, the relatively low fMAX is caused by additional parasitic loading of a thermal via. The starting epitaxial material is also to blame, because it causes higher base resistance and capacitance between the base and collector.

Interconnects between the silicon CMOS and InP transistors have low resistive loss and a high yield.

Heterogeneous integration
The data produced by HRL came from the combination of a 3-inch InP DHBT wafer and a 200 mm CMOS wafer.

Heterogeneous integration began by bonding the epi-surface of the InP wafer, which features an additional 160 nm InGaAsP/InP composite etch stop below the sub-collector, to a handle wafer.

The InP substrate and etch stop layers were removed, and a 0.5 Âµm thick aluminum heat spreading layer was added that bonds this wafer to the CMOS wafer.

A laser trimmed the CMOS wafer to a 3-inch diameter, before the handle was removed.

Finally, standard processing techniques were used to fabricate the InP DHBTs and the heterogeneous interconnects.

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