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100-core Processor Announced By Tilera

World's first 100-core processor sets new benchmark

Tilera Corporation has announced its new TILE-Gx family - four new processors from Tilera including the world s first 100-core processor: the TILE-Gx100. The TILE-Gx100 offers the highest performance of any microprocessor yet announced by a factor of four. Moreover, the entire TILE-Gx family raises the bar for performance-per-watt to new levels with ten times better compute efficiency compared to Intel s next generation Westmere processor. And Tilera has simplified many-core programming with its breakthrough Multicore Development Environment (MDE) together with a growing ecosystem of operating system and software partners to enable rapid product deployment.


The TILE-Gx family employs Tilera s architecture that scales well beyond the core count of traditional microprocessors. Tilera s two-dimensional iMesh interconnect eliminates the need for an on-chip bus and its Dynamic Distributed Cache (DDC) system allows each cores local cache to be shared coherently across the entire chip. These two key technologies enable the TILE Architecture performance to scale linearly with the number of cores on the chip - a feat that is currently unmatched.


“"The launch of the TILE-Gx family, including the world s first 100-core microprocessor, ushers in a new era of many-core processing. We believe this next generation of high-core count, ultra high-performance chips will open completely new computing possibilities," said Omid Tahernia, Tilera s CEO. “Customers will be able to replace an entire board presently using a dozen or more chips with just one of our TILE-Gx processors, greatly simplifying the system architecture and resulting in reduced cost, power consumption, and PC board area. This is truly a remarkable technology achievement."

 


Tilera s breakthroughs in scalable multicore computing are changing the model of computing. Many-core processors enable a wide range of new opportunities including

Consolidation of functions: A single many-core processor can absorb functions that previously required multiple processors, thus lowering system cost and providing a single software tool chain and programming model for developers.


 “At various points in microprocessor history there have been breakthroughs that have enabled significant advances in computing, such as when the barrier of single-core clock speed was overcome by the introduction of multicore," said Sergis Mushell, principal research analyst, Gartner. “Cloud computing and virtualization have ushered in a new era of processing power optimization and utilization, which has accelerated the roadmaps for multicore architectures and changed the paradigm from a clock frequency discussion of the past to a new discussion about number of cores and core optimization."


The TILE-Gx family is fabricated in TSMC s 40nm process, operates at up to 1.5 GHz with power consumption ranging from 10 to 55 watts. The processor family incorporates many cores on a single chip together with integrated memory controllers and a rich set of I/O. However the TILE-Gx device also brings together a number of new features to maximize application performance while offering the best performance-per-watt in the industry. Some of the technology highlights include next-generation 64-bit core: New three-issue 64-bit core with full virtual memory system. Each core includes 32KB L1 I-cache, 32KB L1 D-cache and 256KB L2 cache, with up to 26MB total L3 coherent cache across the device.


On-chip MiCA (Multistream iMesh Crypto Accelerator) system delivers up to 40Gbps encryption and 20Gbps full duplex compression processing, tightly coupled to the iMesh for extremely low latency and wire-speed small packet throughput. In addition, a high-performance true random number generator (RNG) and public key accelerator enable up to 50,000 RSA handshakes per second. Packet processing accelerator: mPIPE (multicore Programmable Intelligent Packet Engine) system provides wire-speed packet classification, load balancing and buffer management. This flexible, C-programmable engine delivers 80 Gbps and 120 million packets-per-second of throughput for packets with multiple layers of encapsulation.

 

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