Mantech Reflects Its Roots
Increasing GaAs fab throughout, streamlining carrier mobility measurements on pHEMT production wafers and suggesting new ways to improve the performance of this class of transistor featured in this year’s CS-Mantech. Richard Stevenson reports.
During the middle of the last decade the GaAs-Mantech conference changed its name to CS-Mantech to reflect the expansion of materials used by III-V chipmakers. Since then presentations at this meeting have covered a wider variety of topics, but conference proceedings are still dominated by papers about the manufacture of GaAs transistors. This year was no different, and the delegates that headed to Portland, Oregon, in mid-May, were fed a diet with a large dollop of GaAs. Here we’ll look at four of those papers: Skyworks Solutions’ account of its fab upgrade to 6-inch; RFMD’s non-destructive method for measuring mobilities and sheet charges in pHEMTs; Hitachi Cable’s study of pHEMT degradation in BiHEMTs; and the development of a high-frequency HEMT, which was led by researchers at the Indian Institute of Technology–Kharagpur.
Boosting fab throughput
The first of these papers detailed the 4-inch to 6-inch conversion of Skyworks’ Newbury Park fab, which processes GaAs HBT and BiFET epiwafers into finished product. Glenn Hafer revealed that these changes led to a 61 percent increase in four inch equivalent throughput, and a 140 percent hike in die production.
Upgrading the fab was not easy, because conversion had to take place in the existing, fully consumed cleanroom space. In addition, full production output had to be maintained throughout the process, along with no drop in the quality of service provided to every customer.
Implementing the fab upgrade involved the introduction of 27 new tools, plus conversion of another 145 from 4-inch to 6-inch, 8 of which had to be relocated. Switching to the larger wafer size also required development of 51 new 6-inch process recipes to new equipment platforms.
Conversion to the 6-inch fab kicked-off with a high-level, top-down plan that identified the critical phases in the project. A ground-level plan followed, which identified every task needed to complete the fab upgrade. This involved input from every engineer responsible for a particular tool and its process. Once this exercise was complete, it appeared that the entire project could take up to three years; the management wanted it rolled out in just two. So to hit the shorter deadline, the project plan was optimized, with more tasks performed in parallel.
To break this large project down into more manageable steps, different staff managed different aspects of the conversion program. By working on smaller projects, those in charge could focus on the finer details.
To keep everyone fully aware of progress, the company held many meetings. Bi weekly meetings kept senior management informed of progress; various weekly meetings aided internal communication, such as that between factory staff and their managers, or project and program managers; and a daily “9 a.m. 6-inch meeting" helped the company execute efficient production while maintaining project progress. “The number of meetings might seem like overkill, but without them this project wouldn’t have been successful," says Hafer.
As the project progressed, tools had to be converted back and forth on many occasions between 4-inch and 6- inch processing. If the technicians were unaware of the latest change, they might have tried to run a process on a tool that was now unsuitable for that task, and wasted good material. To prevent this from happening, a continually updated status for every tool was provided to technicians using a web based approach.
The day of reckoning arrived when Skyworks tested its first devices produced on its 6-inch line. If failure rates were high, the trouble-shooting needed to remedy this could have taken the company beyond its two-year goal for completing the project. But results were excellent: final test yields for transistors from the first two processes run on the new line were 97.2 percent and 98.0 percent.
Skyworks’ biggest rival, RFMD, has also been improving its production process by introducing a Lakeshore multifield Hall system. This tool allows the company to measure non-destructively, rather than destructively, mobilities in the channel and the cap of a pHEMT plus the channel sheet charge (see Figure 1). Keeping an eye on channel mobility is important, because if it falls too low, this can degrade the transistor’s maximum drain current and its drain-source current. However, it is paramount to keep the channel sheet charge close to its target value, because this gives a direct indication of the pinch-off voltage for the FET once the wafers are processed.
Figure 1. RFMD’s pHEMT has two conducting layers: the channel and the cap. It is possible to measure the mobilities in both these layers with a Lakeshore 7612 multi-field Hall system
The lead author of the paper, Robert Yanka, told Compound Semiconductor that carrier mobility in the channel also provides an indication of the condition of the growth system. “When an MBE system is being qualified following a maintenance cycle, mobility can start off low and will rise as the system cleans up. We have specs that let us know when the material is acceptable for delivery to the fab."
Conventional methods for measuring sheet charges and mobilities, such as non contact sheet resistance approaches and single-field Van der Pauw Hall measurements, are unsuitable for pHEMTs because they fail to distinguish between the high mobility carriers in the channel and the low mobility carriers in the cap. Common ways to determine the sheet charge and carrier mobility in the channel are to either etch away the cap prior to measurement, or to use a specially grown test structure that enables direct measurement of channel properties. Neither approach is ideal. It’s not just the added cost that stems from either destructive testing or the growth of additional structures: if the cap is too thin, the depletion layer extends into the channel, and measurements of channel carrier density are underestimated; and if the caps too thick, it contains residual carriers, leading to an overestimate of the channel carrier density.
Multi-field Hall measurements can overcome these issues. The paper presented by Yanka and his co-workers details measurements made on 6-inch wafers produced in a series of runs using magnetic field strengths from 3kG to 15kG and spring-loaded probe pins tinned with indium, which can be “blasted" with a voltage pulse to form an ohmic contact (see Figure 2).
Figure 2. Engineers at RFMD investigated how changes in the excitation current can effect the recorded values of: Channel sheet resistance (Chan Sheet); channel mobility (Chan Mobility); cap sheet resistance (Cap Sheet); and the mobility in the capping layer (Cap Mobility)
RFMD’s engineers use the Lakeshore tool for qualification of MBE reactors following a maintenance cycle. Historical calibrations get the MBE system close to target using multi-field Hall characterization, before a series of three wafers with high, low and nominal doping are then sent for processing to provide the data necessary to finalize the target sheet charge. Growth of product follows, with electrical channel characteristics monitored via Hall measurements on three or four wafers per day.
By monitoring the channel sheet charge density and the pinch-off voltage of processed devices, it is possible to fine-tune the temperature of the silicon effusion cell and produce wafers well within spec (figure 3). Thanks to this feedback, RFMD greatly reduced the number of off-target wafers dispatched for processing.
Figure 3. The rapid feedback provided by the Lakeshore 7612 multi-field Hall used measurements from this instrument to adjust the temperature of the silicon cell, and bring the pinch-off voltage back into the center of the spec. Note the following: the pinch-off voltage and channel sheet resistance values have been normalized; in both cases the data presented is a five-wafer rolling average; and the sign of the pinch-off voltage has been flipped during the normalization process
Optimizing BiHEMT epitaxy
Despite the poor state of the global economy, handset sales are rising again, with the biggest gains in the Smartphone sector. These feature-rich mobile devices incorporate multiple bands and multiple modes, leading to high levels of power consumption and a high chip count. To minimize battery drain and GaAs real estate, some chipmakers have developed processes to unite HBTs with either FETs or pHEMTs. This includes Hitachi Cable, which has been developing a BiHEMT process to unite HBTs and pHEMTs since 2003.
At this year’s CS-Mantech, Junichiro Takeda and his coworkers detailed one of the problems that they uncovered when developing the growth process for this product: a reduction in the carrier mobility in the InGaAs channel of their pHEMT from 7000 cm2/Vs to 5800 cm2/Vs when this transistor was inserted in their BiHEMT structure (see Figure 4 for details of the device architecture).
Figure 4. Engineers at Hitachi Cable studied a BiHEMT structure with silicon-doped layers
To expose the cause of this drop in mobility, engineers used a variety of measurements to compare the pHEMT in the BiHEMT structure with a standalone device. Photoluminescence (PL) measurements produced a peak with the same energy in both structures, indicating that the channel in both pHEMTs had an identical thickness and indium concentration, a conclusion subsequently confirmed by X-ray diffraction measurements.
The PL intensity in the BiHEMT structure was weaker than that from the standalone pHEMT, indicating either an increase in the density of non-radiative recombination centers, or a fall in carrier concentration in this trench. Hall measurements revealed which of these two possible scenarios was to blame: The channel carrier concentration was unchanged, implying that the fall in mobility was probably caused by an increase in defects or impurities in the channel.
The engineer’s next step was to determine whether pHEMT degradation was caused by HBT overgrowth in particularly, or just the thermal history associated with this growth. To answer this question, pHEMT epiwafers were heated under arsine for between 10 and 90 minutes at the temperature employed for HBT growth. Measurements of carrier mobilities and doping profiles revealed a shocking result: Even though the HBT is grown at a lower temperature than the pHEMT, growth at this temperature can still impact the location of carriers, leading to a broadening of the carrier concentration profile and a reduction in carrier mobility in the channel.
To determine the origin of this carrier broadening, the engineers studied their samples by secondary ion mass spectroscopy (see figure 5). This revealed that indium, phosphor, and aluminum atoms were unaffected by heating. Silicon, however, an element renowned for its low thermal diffusion coefficient, spread out from the δ- doped layers and into the AlGaAs spacer layer and InGaAs channel, where it degraded carrier mobility.
Figure 5. Annealing a pHEMT wafer under arsine at temperatures associated with HBT growth causes diffusion of the silicon dopant
Takeda and his co-workers offered two suggestions for improving δ-doped pHEMTs with a high silicon concentration : increase the spacer layer thickness between the channel and electron supply, which invokes the penalty of a cut in the transistor current; or turn to a uniformly doped electron supply layer.
More and more countries are developing III-V expertise, and this year a partnership between researchers from India Institute of Technology - Kharagpur and National Chiao Tung University, Taiwan, presented a paper on the development of an InAlAs/InGaAs HEMT with a novel composite channel. This transistor could be used to make a W-band power amplifier for radar applications.
The researchers aimed to improve HEMT performance by increasing indium content in the InGaAs channel, which leads to several benefits. It deepens the quantum well, confining more carriers to the channel, it almost eliminates three-dimensional carrier movement, and it enhances mobility via a reduction in the electron’s effective mass.
To realize a high-indium-content channel that is free from phase separation, the researchers developed transistors with penta-composite channels that featured graded layers with differing indium content. These structures accommodated lattice mismatch between the layers, and through optimization of indium fraction in the InGaAs layer, δ-doping and spacer thickness, they promise to deliver high currents with good linearity at high frequencies.
The engineers best results were realized with a HEMT featuring an In0.78Ga0.22As channel and a total channel thickness of 14 nm (see Figure 6). This transistor had a drain current of 1029 mA/mm and a transconductance of 648 mS/mm. The device’s cut-off frequency and maximum oscillation frequency were 125 GHz and 250 GHz, respectively, values that the team describes as “remarkable", given the gate length of 0.25 mm. This is much larger than that used by today’s fastest transistors.
Figure 6. A partnership between researchers India Institute of Technology - Kharagpur and National Chiao Tung University, Taiwan has developed novel pHEMT architectures.
If the team goes down this scaling route and makes progress, then it may well be taking part at next year’s CS-Mantech. If this meeting is anything like the last few years, there’s bound to be a good number of GaAs related papers presented in Palm Springs, CA, in mid-May 2011.