News Article
SEMATECH Gate-Stack Symposium Discusses Progress on III-V MOSFETs
Progress is being made on Ge and III-V alternative channel material devices, although this area will require more effort and more resources to demonstrate manufacturable solutions.
Participants at the recent 7th Annual International Symposium on Advanced Gate Stack Technology discussed strategies for implementing advanced logic and memory technologies for sub-16 nm node and beyond process technologies.
The Symposium, hosted by SEMATECH, drew more than 100 international researchers from industry and academia that shared recent discoveries and outlined new gate stack strategies for the 16 nm technology generation and beyond.
"We are very pleased with the global participation in the conference, and with the outcome - in the exploration of solutions for functional stacks for future devices," said Paul Kirsch, SEMATECH's director of front end processes.
"The Symposium's success can be attributed to the breadth and depth of its participants and their research findings. SEMATECH will continue to work collaboratively with the industry on fundamental issues on extending CMOS logic and memory technologies," he continued.
The technologies covered included III-V high performance MOSFETs and high-k/metal gate stacks for Silicon Germanium (SiGe).
Progress is being made on Ge and III-V alternative channel material devices, although there was general acknowledgement among Symposium attendees that this area will require more effort and more resources to demonstrate manufacturable solutions.
Various presenters addressed the functional stack challenges for logic and memory centered on high-k metal gate for Si, SiGe as well as concerns over III-V high performance MOSFETs.
Consensus of the participants is although there are many hurdles to overcome, vertical stacking seems the most promising pathway for continued scaling. To offset the slowdown in scaling and achieve uniformity and address reliability, newer, more innovative materials and switching mechanisms of non-volatile memories need to be investigated further.
Keynote presenters, from Intel's Technology and Manufacturing Group and Macronix provided a comprehensive overview of transistor scaling options beyond the 15 nm node and the challenges of non-volatile memories including floating gate for planar and non-planar devices.
High-k / metal gate process issues were discussed by Sony, Toshiba, IBM and GLOBALFOUNDRIES, highlighting issues with stack scaling.
Andrew Kummel of the University of California, San Diego discussed the density-functional theory (DFT) simulations suggesting practical pathways to improve the quality of high-k oxides on both Ge and III-V interfaces. The impressive progress on Spin Torque Transfer (STTRAM) was discussed by Grandis, Everspin and the University of Virginia.
Several presentations explored new or alternative materials and architectures beyond CMOS devices for 2020, including electron spin devices, graphene, and nanowire transistors. Professor Kang Wang of University of California at Los Angeles reported efficient spin injection into Ge was realized using magnesium oxide (MgO) and is being optimized for spin transfer torque.
The International Symposium on Advanced Gate Stack Technology is part of the SEMATECH Knowledge Series, a set of public, single-focused industry meetings designed to increase global knowledge in key areas of semiconductor R&D.
