Research Review: Novel Gate Boosts Breakdown Voltage
CHINESE ENGINEERS have increased the breakdown voltage of a SiC MESFET by switching to a multi recessed gate with an etch depth of 80 nm.
These efforts by the team from the University of Electronic Science and Technology of China, Chengdu, and The National Key Laboratory of ASIC, Shijiazhuang, will help to raise the profile of SiC MESFETs. These transistors are promising candidates for use in military and commercial communications that require components operating at high frequencies, high powers and high temperatures.
The researchers are developing transistors based on SiC, rather than GaN, because the former is more robust at higher temperatures: “At present, commercial GaN
RF devices struggle to meet the strict reliability requirements for military and commercial applications, especially for applications requiring high temperatures," says lead-author Xiaochuan Deng.
In the past, SiC MESFET performance has been held back by trapping issues associated with the surface and the layers under the active channel. “Recently, concern has shifted towards surface traps, due to the introduction of high-purity semiinsulating substrates that have eliminated most of the trapping problems associated with the substrate and the interface between the substrate and p buffer," explains Deng.
By turning to a multi-recessed gate, he and his co-workers have directed the current path in the on state away from the surface, leading to less electron tunnelling and trapping near this region.
MESFETs with a 0.8 μm gate length and a 250 μm gate periphery were made on highpurity semi insulating substrates produced by Cree. At a drain bias of 65 V the transistors – which featured a 2.5 μm-thick p-buffer with a doping level of 5 x 1015 cm-3 and an n-type, 0.3 μm-thick active layer with a doping level of 2.3 x 1017 cm-3 – delivered an output of 33.5 dB, a linear gain of 8 dB, and a power added efficiency of 30 percent. These results were realised when the RF input to the MESFET consisted of 2 GHz, 50 μs pulses with a 5 percent duty cycle.
The team has recently built a 20 mm gate periphery SiC MESFET. At a drain voltage of 80 V, this produces a saturated output power of 94 W at 3.4 GHz. Deng says that in addition to developing these large periphery MESFETs, the team is focusing on improving the power-added efficiency of its transistors, because many applications demand high power over a wide bandwidth.
X.C. Deng et al. Electron. Lett. 47 517 (2011)