Technical Insight
Multiple materials enhance front-ends
The front-ends of smartphones should not be served by a single material. Instead, to ensure sufficient performance, they should combine a GaAs-based power amplifier with a silicon-on-insulator switch and filters made from piezolelectrics
BY JAMES YOUNG FROM SKYWORKS
Many of us feel lost without our mobile phone. In one form or another, we have been taking them with us on a daily basis for many years, and as time has gone on, we are probably using them more than ever. In the past, we made calls and sent texts, but now these portable devices are also used for listening to music, surfing the web, and watching videos.
To improve the experience of the user, every generation of mobile phone operates at a higher data rate than its predecessor. Due to this advancement, network data is growing at an exponential rate. What's more, there is an every-increasing complexity in the handset's RF front-end. It is packed with filters, switches and power amplifiers that are meeting more demanding specifications than ever before.
Another major change in the design of the RF front-end is the shift from discrete components to highly integrated products. This evolution has made life easier for the makers of handsets, but more challenging for their suppliers that are faced with designing more complex products. Two distinct approaches have been adopted "“ the system-on-chip and the system-in-package "“ and both can feature compound semiconductor and silicon content. In the remainder of this article we will evaluate all these technologies, before considering the make-up of a state-of-the-art front-end module that combines affordability with great performance and a small footprint.
One of the essential requirements for an RF front-end is that it can cope with the exponential growth in data that has underpinned the expansion of new standards and bands (see Figures 1 and 2). The introduction of 4G has provided a ten-fold increase in the mobile handset data rate, but if no new bands were added to the network, this additional capacity would be consumed in just three-to-five years. To address this, high-end smartphones are now being packed with more and more bands (see Figure 3). Changes such as this increase the complexity of the RF front-end, and products with high levels of integration, are needed to overcome issues related to efficiency, size, cost and time-to-market.
Figure 1. Throughout this decade, mobile data traffic is increasing at an exponential rate.
Examples of the complexity of the modern RF front-end include the need to support 13 to 24 4G bands and be capable of handling carrier aggregation (see Figure 4 for a front end block diagram). These requirements must be met with a product offering high efficiency, to ensure a long battery life for the smartphone.
To extend the battery life the phone must be efficient at converting the battery energy to RF energy transmitted out of the antenna. Any loss of energy in the PA and after the PA will reduce the battery life. Dominating losses are those occurring at: the duplexer/filter; the PA transistor; and the passive components, including the matching networks and the carrier aggregation functions (see Figure 5). We will now assess all of these areas in turn, in an effort to highlight the best technologies for delivering great performance from a small, low-cost product.
Superior switches
Key characteristics for judging the quality of the switch are its insertion loss, level of isolation, linearity, cost and size. When designing this component, it is essential to consider the standing-wave RF voltage across the switch when it is delivering its maximum output power. In extreme cases, which can occur when there is a high mismatch-impedance at the antenna, the voltage across the switch can peak at just over 70 V. This is enough to damage a single transistor. High levels of voltage across a transistor can also generate harmonic levels that lead to unacceptable performance.
To overcome these limitations, multiple devices are stacked in series. This approach splits the voltage across multiple transistors. For example, when transistors are made with a 0.18 µm MOSFET SOI process, between 8 and 12 devices typically form a switch. This can be reduced to roughly three devices by using a dual-gate PHEMT, thanks to its higher breakdown voltage.
Figure 2. Introducing new mobile standards and bands enablesan increase in data rates.
Once the transistor technology and stack has been chosen, an engineer must select the width of each FET, a decision that determines the off capacitance and the off RF isolation. The isolation must be between 25 dB and 30 dB to ensure that the off arms do not disturb the performance of the on arm.
The width of the FET also dictates the on-resistance of the switch, and this in turn governs the RF insertion loss. A comparison of different technologies for a nine-throw antenna switch shows that MEMS provides the lowest insertion loss (see Figure 6). However, the silicon-on-insulator devices with a slightly higher insertion loss (they are still superior to those based on GaAs PHEMTs) are used because they provide the highest level of integration at a low cost.
Fantastic filters
An ideal filter would reject all frequencies outside a particular band, while passing those within it with minimal loss. In practice, this is not possible "“ a typical passband response for a duplexer is shown in Figure 7. Note that decreasing the spacing between the transmit passband and the receive passband enables more efficient use of the frequency spectrum, but requires more resonators to achieve the out-of-band attenuation. Doing this has a downside, as it leads to a rise in insertion loss. Note that the typical requirements for a high-performance duplexer are a transmitter isolation in the receive passband in excess of 55 dB, and an insertion loss in the transmitter and receive passbands of less than 2 dB.
Comparing the different approaches to making filters shows that devices based on surface acoustic wave (SAW) technologies are needed to meet the requirement for an insertion loss of less than 2 dB (see Figure 8). Although this is by no means the lowest cost approach, it is implemented, because filters are a significant contributor to the overall front-end energy loss between the power amplifier output and the antenna.
Filters configured as a diplexer, triplexer or quadplexer are also used to connect multiple bands at one time to the antenna. This is done to support carrier aggregation, which allows two or three bands to simultaneously operate over a common antenna.
This approach is illustrated in Figure 4, which shows mid- and low frequencies combined through a diplexer, and high-band frequencies operating via a separate antenna. It is a design that allows three bands to be active at one time, and when the diplexer is formed with a printed circuit board or a low-temperature, co-fired ceramic technology, insertion loss is around 0.4 dB.
The downside of using two antenna is that it consumes more space "“ so designers may prefer to triplex the three bands and reduce the number of antennas to one. But with a single antenna, the mid- and high bands are very close together, causing a high loss at the diplexer or triplexer. If this were made with a low-cost, printed circuit board, lumped element or low-temperature co-fired ceramic technology, the typical insertion loss would be 1.5 dB. That's considerable, as offsetting this loss would require an increase in the output of the power amplifier by 1.5 dB "“ and that equates to a 40 percent hike in the current consumed by this amplifier. That is a high price to pay for a single antenna design, and explain why many handsets incorporate multiple antenna.
Figure 3. To improve the rate of data transfer to a smartphone, the number of 3G/4G bands that it incorporates is increasing.
Attractive amplifiers
The key attributes for a successful power amplifier are a high power-added efficiency, small size and low cost "“ and excellence in these areas must be accomplished while maintaining other system specifications. To optimise amplifier efficiency, engineers must carefully select the class of operation, load line impedance, transistor size, and bias.
Another decision for engineers of front-end systems is to choose between one of two control systems for improving the efficiency of the amplifier: average-power tracking, which operates the amplifier in its linear region; and envelope tracking, which operates the amplifier in gain compression or in saturation.
With the former approach, where the amplifier is run in a linear regime, the saturated output power is set high enough to pass the peaks of the waveform with minimal distortion. As the peak-to-average power increases, the average power is set further below the maximum saturated output power of the amplifier. The difference between the average power and the saturated power is referred to as the "˜back-off' power. At higher data rates, the peak-to-average waveform is higher, so the back-off power is higher, reducing the efficiency of the amplifier.
The common alternative to this, envelope tracking, is centred on two fundamental concepts: that the amplifier's maximum saturated output power is proportional to the supply voltage; and that the power-added efficiency of the amplifier is highest when it is saturated. So, for an amplifier operated with envelope tracking, the load line is calculated and fixed, based on the maximum peak output power to be transmitted at the maximum rated supply voltage. Once the value for the load line has been set, the saturated output power is varied by changing the supply voltage, so that it tracks the envelope of the signal.
It should be noted that with an envelope tracking system, the minimum voltage that can be applied to the drain or collector of the transistor limits the range of power that can be tracked. The minimum voltage is typically around 1 V, and below this the gain of the transistor drops to unacceptable levels. Due to this, the range of the RF envelope output power that the envelope tracking system can track tends to be around 12 dB, and this limits the average output power tracking to the top 6 dB to 10 dB of output power. Fall below this range and the efficiency of the envelope tracking system drops, shifting the amplifier's mode of operation to average-power tracking in a linear regime.
Another decision that an engineer must consider is the class of operation for the amplifier. Amongst the many options, a class F load is popular, because it produces a higher efficiency at a given linearity.
To realise class F operation, the collector voltage and current waveforms are shaped with harmonic traps or resonators in the output network. This modifies the voltage waveform to approximately a square wave, and the current waveform to approximately a half-sine wave. Realising this involves presenting a short to the collector at even harmonics, and an open at odd harmonics.
The efficiency of an ideal class-F power amplifier increases with the number of harmonic terminations. Producing a high-efficiency output network might appear taxing, but in practice only the first few harmonics need to be correct. When size and cost considerations are taken into account, optimal termination of just the second and third harmonics tends to suffice.
Envelope-tracking amplifiers have been operated in both Class F and Class E. Higher efficiencies are possible with Class E, because with a simple output network, the collector waveforms are properly shaped. However, when the system drops back to average-power tracking, class F provides superior linearity.
Figure 4. A typical mobile front-end block diagram, which has been taken from Skyworks "˜SkyOne' products. Note that this particular configuration allows the user to combine the high, mid- and low bands external to the package as the user desires.
GaAs or silicon?
One debate that is going on within the amplifier sector is whether the incumbent technology, the GaAs HBT that holds over 95 percent of the market, will lose market share to devices based on CMOS and silicon-on-insulator technologies.
Comparing the strengths of these competing technologies is straightforward once we have established the power-added efficiency operating points for average-power tracking and envelope tracking. Plots of power-added efficiency as a function of output power can highlight the differences in efficiency between the different material technologies and the different modes of operation.
One such plot is shown in Figure 9, which is for a two-stage power amplifier operating with a range of supply voltages. The collector voltage, which is essentially the same as the drain voltage for a FET, is modulated to vary the saturated output power. Different supply voltages produce different curves. For comparison, the maximum drain or collector voltage used in this example is 3.5 V which is the mobile phone battery voltage. This implies that the saturated output power at 3.5 V will be equal to the amplifier's maximum peak output power.
Based on these assumptions and findings, it is possible to consider the operating conditions for different forms of data transmission. For a WCDMA voice waveform with a 3.5 dB peak-to-average power ratio, the average operating point will be around 3.5 dB below Point A (this is labelled in Figure 9 as the "˜Voice Mode ET' operating point). It can be seen from the graph that the average envelope-tracking voice operating point at the maximum output power would have about a 4 percent power-added efficiency below point A, and have an average modulated collector voltage of about 2.3 V.
When the mode of operation is average-power tracking, the collector voltage must remain at 3.5 V to support the WCDMA voice waveform peaks. However, the average operating point of the amplifier will follow the black dotted line in Figure 9, which is labelled "˜Linear PA' and is 21 percent below point A. This highlights the inferiority of average-power tracking "“ for voice mode, the power-added efficiency is 17 percent lower than that for envelope tracking. The data shown in Figure 9 is based on measurements on a specific power-amplifier, and a different design may change the absolute value of point A. While the absolute efficiency, or starting Point A, will vary from one amplifier design to another, or from one technology to another, the relative difference in efficiency from Point A will change very little. So the absolute efficiency, or starting Point A, will vary from PA design to PA design, and from technology to technology, but the relative difference in efficiency from Point A will remain close to the same.
Another comparison that can be made is to consider efficiencies associated with data, rather than voice. Assuming an LTE data operating point with a peak-to-average waveform of about 6.25 dB, the power added efficiency for average-power tracking is 22 percent less than that for envelope tracking (see Figure 10).
Armed with knowledge of the relative changes in power-added efficiency to point A simplifies a comparison of the various technologies. Point A has been calculated for a two-stage power amplifier, a form of design found in many handsets (see Figure 11 for details).
Relatively simple calculations based on this approach allow a comparison of HBT, silicon-on-insulator and CMOS technologies (see Table 1). While the power-added efficiency of amplifiers based on silicon-on-insulator technology have shown incremental improvement over time, with ST setting a new benchmark with an 80 percent drain efficiency, amplifiers based on the GaAs HBT are ahead by a considerable margin, and are getting even better with time. At first glance, the primary appeal of the silicon amplifier would thus be its apparently lower cost. But that's not the case: System-on-chip silicon amplifiers have die sizes that are three to five times bigger than those of GaAs HBT die, which means that the latter combines higher performance with lower cost.
Figure 5. A breakdown of the causes of efficiency lost during converting DC to antenna RF. Note that the passive components include the matching networks (MN) and the carrier aggregation (CA) function.
Figure 6. For a nine-throw antenna switch, MEMS technology offers the lowest insertion loss. However, silicon-on-insulator (SOI) technology has an acceptable insertion loss and is significantly cheaper, so this dominates the market today.
Figure 7. A typical passband response for a duplexer.
Figure 8. The higher the quality factor (Q), the lower the insertion loss for a band 2 transmitter filter designed to maintaining the specified receiver band isolation. It is clear that discrete filter implementations with inductors implemented in printed circuit board, low-temperature co-fired ceramic or chip form with quality factors around 40-50 would have far too high an insertion loss. Also noted are tunable technologies. But their quality factor is also too low. In order to have an insertion loss of less than 2 dB, a high quality factor realised with a SAW or FBAR process is required.
A marriage of materials
This survey highlights the need to pick the best technology for each of the elements within the front-end of a mobile device. Take this approach, and silicon-on-insulator switches are combined with SAW filters and power amplifiers made from GaAs HBTs.
The alternative, system-on-chip approach cannot exploit a material that excels in all areas. The leading candidate is silicon-on-insulator, but it cannot integrate the filter on die. What's more, the assumption that a system-on-chip approach leads the way in terms of cost and a small footprint does not hold true for the RF front-end.
Figure 9. Envelope tracking (ET) enables a far higher efficiency than average-power tracking for Voice Mode OP. Note that one can estimate the efficiency for various waveforms by moving down the ET or Linear PA operating curve from point A by the peak-to-average power of the new waveform.
Figure 10. For Data Mode OP, envelope tracking (ET) provides a 22 percent higher power-added efficiency than average-power tracking (APT).
Figure 11. A typical multi-stage power amplifier. In this diagram, PIN is the RF input power, ηM is the match efficiency, ηC is the collector or drain efficiency, PC is the RF collector or drain power, POUT is the RF output power, and PB is the RF base of gate power. Values for all these can be fed into relatively simple equations to calculate the power added efficiency. See Table 1 for results obtained in this manner.
With the system-in-package architecture, the amplifier output match can be moved into the low cost laminate, and the power amplifier bias into a low-cost CMOS process. This creates a cheaper product that is also smaller, thanks to the reduced dimensions of the amplifier die. An additional strength of this design is the opportunity to stack CMOS and HBT die with three-dimensional packaging, a step that saves more space.
The system-in-package front-end will continue to improve, as new features are added with each generation of product. Receive carrier aggregation is now being incorporated, and soon this will be twinned with transmit carrier aggregation. Other refinements that are anticipated are an increase in receiver sensitivity and a reduction in the transceiver pin count, achieved by moving the low-noise amplifier next to the duplexers and into the front-end package.
The front-end design will continue to evolve, and system-in-package flexibility will allow it to quickly respond to market changes, enabling potential customers to quickly sample new products.
