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A Critical Look At InGaAs MOSFETs

Does InGaAs have the right set of attributes for maintaining the march of Moore's Law?
Moving from one node to the next is getting ever harder. Back in the twentieth century, progress just involved shrinking the size of the silicon transistor. But since the turn of the millennium, it has required major modifications to device design to maintain performance improvements with scaling. Changes to the transistor architecture have included: straining the channel, by inserting germanium into source and drain regions; switching the gate dielectric from silicon dioxide to hafnium dioxide to prevent leakage currents from escalating; and introducing a three-dimensional finFET to help the gate maintain control over charge carriers in the channel. Further refinements are sure to follow, and may well include the introduction of new channel materials that sport a higher mobility. For the pFET, germanium is the most likely successor for the channel, while for the nFET it is some form of In(Ga)As âˆ' In0.53Ga0.47As, or InAs layers, or In0.53Ga0.47As/InAs laminates.
At first glance, these channel replacements have a lot going for them. Compared to silicon, In(Ga)As has a higher mobility and lower effective mass. Consequently, introducing this material could enable electrons to zip through the channel as faster speeds, and ultimately allow devices to operate at a lower voltage while maintaining the currents of the predecessors. That is a big deal, as it would allow an IC to maintain its power consumption while increasing transistor count, and ultimately lead to improvements in the performance and capability of battery-powered mobile devices, such as smartphones and tablets.

However, this line of reasoning might be too simplistic, as it might be the case that introducing higher mobility materials will fail to deliver increases in transistor performance at shorter nodes. At long gate lengths this will not be observed: in this regime, it has already be proven that the on-current of the FET is proportional to the electron mobility, and it increases when a silicon channel is replaced with one made from a III-V. But in leading modern VLSI technologies, gate lengths are 20 nm or below and the on-current is not strictly mobility-limited. Instead, at the limit of extremely short gate lengths, transport approaches the ballistic limit. In this regime, the transistor on-current is determined by the injection velocity of electrons into the channel. The low electron effective mass in InGaAs can still lead to larger on-currents than comparably scaled silicon FETs, but whether this is the case depends on the thickness of the gate dielectric and channel.

A more detailed look at the issues reveals that a low electron effective mass is actually a double-edge sword. Although it gives a larger electron velocity at a given kinetic energy, this benefit goes hand-in-hand with a reduction in the number of available quantum states within a given energy range. Due to this, the charge in the channel reduces, according to simulations by Massimo Fischetti from the University of Texas at Dallas. Since the current is the product of charge and its velocity, the reduced charge can offset, in whole or in part, the increase in on-current resulting from increased electron velocity (see Figure 1 for details). However, so long as the combined thickness of the gate dielectric and channel are relatively large, there is an increase in the FET on-current associated with the use of a low-effective mass materials such as InGaAs or InAs. Note that when extremely thin channels and dielectrics are deployed, this benefit diminishes. 

Another insight provided by Figure 1 is that although InGaAs cannot out-perform silicon in the most highly-scaled MOSFETs, the increase of gate leakage current by tunnelling sets a lower limit to the gate dielectric thickness. As this figure assumes a ballistic limit to transport, the relative performance of silicon and III-V transistors also depends on how close these two materials get to this limit. 

Figure 2: The progression of III=V MOSFET designs at UCSB for reduced off-state leakage current.

With silicon, thicker channels lead to the occupation of more conduction-band minima. As these valleys have a higher transport effective mass, on-current is reduced. Meanwhile, with III-V MOS, there are two key requirements for success: a low density of interfacial energy traps at the channel and gate dielectric interface, and the growth of low-defect density InGaAs layers on silicon. Ultimately, however, whether the III-V MOSFET has the upper hand over its silicon counterpart depends of a variety of device characteristics, such as injection velocity, channel mobility, the minimum technologically feasible thicknesses for the dielectric and channel, and source and drain access resistivities. The only way to determine the overall contribution is to undertake an experimental comparison of the two classes of device.

Off-state leakage

One of the biggest concerns surrounding the development of III-V MOS technology is the high off-state leakage current of these devices. The International Technology Roadmap for Semiconductors (ITRS) stipulates a maximum off-state leakage of 100 nA per micrometer of gate width for high-performance (HP) logic, 1 nA/μm for general-purpose (GP) logic, 30 pA/μm for low-power (LP) logic, and 10 pA/μm for ultra-low-power (ULP) logic. HP logic might be used in servers, GP logic in PCs and larger laptops, LP logic in smartphones and tablets, and ULP logic in ultra-long-battery-life devices such as Internet-of-things. 

Figure 3. Transmission electron microscopy cross-section of InAs MOSFET with 2.7 nm InAs channel. Note that heavy elements look brighter. This image is courtesy of S. Kraemer, from UCSB. More details can be found at Lee et. al. 2014 VLSI Symposium

A major challenge facing III-V MOS is maintaining performance during channel and gate dielectric scaling. At long gate lengths, off-state currents arise in part from normal thermally-activated leakage, and sub-threshold characteristics can get as low as the theoretical limit of 60 mV/decade. But at short gate lengths, the sub-threshold swing can be far larger. To prevent this, the gate dielectric and the channel must both be thin enough to prevent any deterioration in the electrostatic control of the channel by the gate electrode. If the gate length in a planar III-V MOS has a length approaching 20 nm, then in order to maintain good electrostatic control, this transistor must have a channel that is no more than 5 nm thick, and the gate dielectric must have an equivalent thickness of around 0.8 nm. For three-dimensional devices, such as finFETs and nanowires, thicker channels and dielectrics are permitted.

One other difficulty facing the developers of III-V MOSFETs is the selection of a suitable material for the gate dielectric. The chosen material must prevent high leakage currents and enable an acceptable density of traps at the dielectric-channel interface. Finding a high-k dielectric for III-V semiconductors has been very challenging, with materials tried-to-date tending to produce high interface trap densities that lead to high sub-threshold swings.

In addition to the challenges of maintaining performance with scaling, and finding a gate dielectric that can lead to a low sub-threshold swing, developers of III-V MOSFETs need to craft devices with a low tunnelling leakage current, because this ensures a low off-state leakage. With InGaAs this is particularly tough: the low bandgaps of InGaAs and InAs cause very high band-to-band-tunnelling (BTBT) leakage currents, and the low effective mass can be to blame for very large source-to-drain tunnelling (STD) leakage currents. In In(Ga)As MOSFETs, both of these leakage mechanisms are pronounced, and get more severe as the gate length shortens. The BTBT may increase, due to a hike in parasitic bipolar current gain, while STD leakage increases due to a shortening of the tunnel barrier.

Low-leakage III-V MOSFETs

Our team at the University of California, Santa Barbara, has been developing III-V MOSFETs for many years, and during that time we have refined the design of our devices (see Figure 2). The four architectures we have produced are different types of planar, ultra-thin-body transistors with either an InGaAs or InAs channel and a MOCVD-regrown, n+ source and drain.

Device fabrication begins by MBE growth, patterning of a dummy gate, and a source and drain recess etch. Source and drain regions are added by MOCVD, before removing the dummy gate and adding a ZrO2 dielectric by atomic layer deposition. A nickel gate is defined by a lift-off technique, before the addition of source and drain contacts completes MOSFET fabrication.

To speed production, and hence development, our transistors are not self-aligned. This means that although we can fabricate gates as short as 10 nm, there are large overlaps between the gate electrode and the n+ source and drain. Note also that our source and drain Ohmic contacts are more than 1 μm from the gated channel. In comparison, production III-V MOSFETs would be markedly different, because they would have: self-aligned gate, source and drain electrodes; nearly vertical sidewalls for the n+ source and drain re-growths; and, to reduce capacitance, a low-permittivity dielectric spacer in the sidewalls between the gate and the n+ source and drain.

The first step to address when lowering the MOSFET off-state leakage is to trim the substrate leakage current (see Figure 2, and compare top left and top right). When this is addressed by vertical confinement of the carriers to the channel by its interface with the bottom barrier, the InGaAs MOSFET has more in common with a silicon planar SOI transistor than a bulk silicon MOSFET. Yet, if the barrier is InAlAs, there is not a sufficiently large obstacle to electron injection from the  n+ InAs or InGaAs source. This hampers device performance, as it can result in significant leakage currents between the source and drain through the bottom barrier. Substrate leakage can be suppressed by inserting AlAsSb barrier layers, which have a higher barrier energy. A simple alternative is moderate p-type doping of the substrate or barrier layers.

The second major mechanism for off-state leakage in III-V MOSFETs is BTBT. This type of leakage is most severe in the high-field region. It can either be prevalent at the drain end of the channel, next to the gate edge, or at the junction between the channel and the regrown heavily-doped drain. Adding a lightly-doped spacer between the  n+ drain and the gate end of the channel can cut the BTBT leakage. This reduces the field and increases the drain-to-channel separation, leading to diminished electrostatic coupling between them. An upshot is improved electrostatic control of the channel by the gate, which enhances the transistor's turn-off characteristics. 

One option for the spacer is a lightly doped lateral gap between the edges of the gate and the n+ drain. However, if the distance of this spacer is a significant proportion of the gate length, this can cut the transistor packing density. A more attractive approach is to insert a lightly-doped semiconductor spacer during the regrowth sequence of the n+ source and drain (see the device in the top right corner of Figure 2).

Further reductions in leakage result from the introduction of an ultra-thin channel (see Figure 2, lower right). Advantages of this include improved transistor electrostatics at short gate lengths, and an increase in the channel bandgap, via quantization, that drives down BTBT leakage.

We have produced a 25 nm gate length device with a 2.7 nm-thick InAs channel with this architecture (see Figure 3). The transconductance for this device, 2.4 mS/μm, is not a record for III-V MOS technology. However, that's not surprising, because thicker channels are needed for a higher transconductance "“ and that comes at the expense of larger off-state leakage currents. 

Figure 4. 2.7 nm InAs channel FET: sub-threshold characteristics at 25 nm gate length.

Figure 5. III-V transitors produced by the team at UCSB deliver a record on-current at a 0.5 V operating voltage.

The DC characteristics for this device include a (minimum) sub-threshold swing of 72 mV/decade (see Figure 4). Residual BTBT leakage is clearly evident, and when the gate is held at -0.3 V bias, the drain current ramps up with increasing drain voltage. Nevertheless, at the target 0.5 V drain bias that is expected to be used in next-generation ICs, the minimum off-state leakage is below 10nA/μm, well within the requirement for high-performance logic. 

When engineers design a VLSI device, they select the gate metal for the appropriate threshold voltage and set the off-state leakage current target value defined in the ITRS. However, when producing an experimental device in a research environment, it is inconvenient to shift the threshold. So, what we do is to numerically shift the threshold voltage in our data (see Figure 5), such that the off-state leakage becomes 100 nA/μm, the ITRS GP logic specification. This allows us  to compute the on-state current at a gate-source voltage 500 mV above threshold (see Figure 5 for the resulting data, which shows, as a function of gate length, the on-current at a specified 100 nA/μm for a 500 mV power supply voltage). 

Figure 6. The sub-threshold swing for the 2.7nm InAs channel FET is very close to 60mV/dec., indicating a high-quality gate dielectric.

Figure 7. Sub-threshold characteristics a InGaAs/InAschannel FET with 13 nm-thick InP source-drain vertical spacers having graded doping. The ZrO2 gate dielectric is 3.8 nm thick, and the gate length is 30nm. The minimum off-state leakage is 60 pA/μm.

Judged from a compound semiconductor perspective, this on-state current is very impressive, because it sets a new benchmark for what is possible with III-V MOS technology. However, the performance at a similar physical gate length is incredibly close to that of a comparably-scaled planar UTB silicon SOI MOSFET made by researchers from STMicroelectronics and the IBM Technology Development Alliance.

While there is no doubt that the ultra-thin channel and vertical spacers for the source and drain play a role in the high on-off ratio of our devices that are shown in Figure 3, the greatest contribution probably comes from the gate dielectric. We use a stack of AlOxNy and ZrO2 formed by atomic layer deposition, a technology that has been developed by colleagues at our university, led by Susanne Stemmer.

The quality of this dielectric is highlighted by the sub-threshold swing for a long-channel device at a low drain bias. It is just 61 mV/decade, a value very close to the thermal limit, and the lowest reported for a III-V MOS technology.

If III-V MOS is to replace silicon in VLSI, it must offer a considerable performance advantage. As we have already stated, that is not the case today, as published state-of-art III-V data is only on par with the performance of the best silicon. However, it is possible that industry, with its superior fabrication resources, can demonstrate a better III-V device. One immediate opportunity for improvement exists in our non-selfaligned FET structure; with no low-εr dielectric spacer between the gate and the N+ drain, leakage currents associated with gate-induced drain lowering (GIDL) are probably far higher in our devices than they would be in a properly self-aligned transistor.

At this stage, our devices at 100 nA/μm are suitable for ITRS HP (high performance but high power) applications. But if InGaAs MOS is to be a viable technology, it must also address at least the GP and LP market segments. The large mobile device markets, in particular, drive the LP and ULP technologies. To be able to meet these lower power requirements, we need to trim our BTBT leakage currents. There must be cuts in both the tunnelling leakage within the channel near the drain junction, and at the channel-drain junction itself. 

One option is to replace the strained InAs channel (Figure 4) with either an InxGa1-xAs channel or an In0.53Ga0.47As/InAs composite channel. These modifications will increase the channel bandgap, leading to a decrease in BTBT leakage within the channel and a reduction in off-state leakage. However, if the In0.53Ga0.47As channel is thinned to less than about 5 nm, transconductance will plummet, leading to a lower on-current. The origin for this degradation is yet to be understood. 

Addressing the BTBT leakage at the gate-drain junction holds the key to further reductions in the off-state leakage currents, which will enable devices to move close to the ITRS LP and ULP targets. This brings us to the final device design (Figure 2, bottom left), which features an undoped, wider-bandgap spacer layer, such as InP. 

We have found that when these spacer layers are thick, this increases the source access resistance of the FET, leading to a lowering of the on-current (see Figure 7). It is possible to lower the access resistance and boost on-current by introducing a doping gradient within the InP spacer. This step ensures that the depleted region within the InP spacer is thinner in the source than in the drain. With this modification, at a drain bias of 0.5 V, the minimum off-state leakage is 60 pA/μm, which is close to the ITRS LP specification. Variations in transistor size do not lead to changes in this leakage, indicating that the figure of 60 pA/μm stems from surface leakage currents arising from inadequate device isolation. The internal transistor leakage current is smaller than this with a magnitude that is yet to be uncovered.

Further improvements in the off-state leakage are possible. According to our data, BTBT leakage can be driven below 60 pA/μm with a 5 nm InP spacer layer. Yet, we employed 12 nm-thick InP spacers, with the aim of maintaining good electrostatics "“ and hence a small sub-threshold swing and DIBL "“ at a 30 nm gate length. The downsides of such a structure are excessive source resistance and a reduced on-current.

A promising candidate for realising success on more fronts is the planar UTB device. If this were constructed with a composite spacer with an upper InGaAs layer and a lower InP layer, it might be able to combine reduced BTBT leakage with good electrostatics at short gate lengths and a low source resistance. Success would require grading of the InGaAs/InP heterointerface to suppress the influence of the barriers. An alternative is the finFET, which has superior electrostatics than the planar UTB, thanks to the double-gated structure. With this transistor architecture, a thin 5 nm InP layer in the drain regrowth would provide adequate BTBT suppression, rendering the additional InGaAs spacer unnecessary.

Figure 8. The structure (a) and TEM cross-sectional image, of a MOSFET with a 1.5nm InGaAs / 1nm InAs channel and a gate length of around 10 nm.

To evaluate what might be possible, we have fabricated In(Ga)As MOSFETs at the limits of the scaling of a planar UTB device. Our goal: to demonstrate that high on/off current ratios can be obtained in III-V MOS technologies, despite the potential for high band-to-band and source-to-drain tunnelling leakage currents associated with low carrier mass and small bandgap energies.

The transistor fabricated for this study has a thin composite channel with a 1.5 nm In0.53Ga0.47As layer and a 1.0 nm InAs layer (see Figure 8). The regrown source and drain regions contain vertical InP spacers with unintentionally doped and graded-doped sections. The gate orientation on the wafer has been rotated by 90 degrees compared to earlier devices, a change that has resulted in more nearly vertical regrowth profiles on the n+ source and drain. 

These refinements have paid dividends. BTBT tunnelling is reduced by the InP spacers and the In0.53Ga0.47. As layer within the channel, while electrostatic short-channel effects and source-drain tunnelling leakage currents are reduced by the device geometric design: the transport path is curved and the channel is U-shaped, resulting in a net transport distance between the source and drain that is substantially larger than the horizontal footprint of the gate.

A curved channel is desirable, because it enables close device packing and enhanced DC performance. That's because the horizontal footprint determines the VLSI device packing density, while the transport distance governs short-channel effects and tunnelling.

DC measurements on our transistors reveal that the sub-threshold swing is too large for a production device (see Figure 9). However, our MOSFETs maintain a good control of off-state leakage, with the drain current varying by a 8.3 x 105:1 on/off ratio as the gate potential is swept from -0.3 V to +0.9 V.

The road ahead

Our efforts, and those of our contemporaries, have been motivated by using III-Vs in the channel, because it provides a low carrier effective mass and high carrier mobilities. Key findings that have emerged from our work include the realisation that if gate dielectrics can be further thinned, the low effective mass of such materials will fail to deliver a larger on-current than would be obtained with a silicon channel. We note, however, that it appears unlikely that gate dielectrics in VLSI can be made much thinner. We have also noted the need to address the low bandgap energies and low carrier masses associated with In(Ga)As, if this is to become a viable channel material in VLSI.

Figure 9. Log(ID)-VGS characteristics of the device of the device shown in Figure 8.

Additional insights by our team are that composite InGaAs/InAs channels with a thickness of just 2 nm to 4 nm can reduce tunnelling leakage in the channel, while the insertion of thin InP source/drain spacers can ensure low band-band tunnelling leakage in the high-field regions near the drain. Requirements for out-performing silicon are to understand and address the current collapse in sub-5 nm InGaAs channels, and to use no more than 5 nm in the drain spacer layers. Options for improving electrostatics are to employ composite InP/InGaAs spacers in planar UTB III-V MOSFETs, or to turn to finFET or nanowire geometries.

Even if III-Vs should not prove to be superior to silicon in conventional MOSFETs, efforts by ourselves and others will not have been wasted, because III-V MOS will remain an important technology for VLSI. That's because the low carrier masses and favourable energy-band alignments make III-Vs the leading contender for low-voltage, low-power tunnel-FET logic.

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