Banishing breakdown in GaN HEMTs
A punch-through gate design equips the E-mode GaN HEMT with an inherent non-destructive breakdown capability.
BY JINGJING YU, JUNJIE YANG, BO SHEN AND JIN WEI FROM PEKING UNIVERSITY
Within the portfolio of power devices, the GaN HEMT is renowned for its high power and high frequency, resulting from a fast switching-speed and low conduction loss. Today, HEMTs with a p-GaN gate are combining enhancement-mode operation with a low on-resistance and a high breakdown voltage, a set of attributes that are attractive for consumer applications, such as fast chargers and class-D audio amplifiers. However, the broader adoption of the GaN HEMT in demanding industrial applications is impeded by its limited robustness against transient overvoltage spikes, common in high-frequency power switching applications.
This weakness is not found in vertical silicon and SiC power devices – they typically exhibit
non-destructive breakdown behaviour under transient voltage overshoots, due to an intrinsic avalanche capability. In contrast, lateral GaN power HEMTs tend to suffer from destructive breakdown, possibly due to the absence of a p-n junction that effectively removes impact-ionisation-generated carriers. Due to this weakness, engineers significantly overdesign the blocking capability of state-of-the-art GaN power HEMTs.
One option for addressing the limited transient overvoltage reliability in GaN transistors is to add snubber circuits that suppress the voltage oscillation. However, this solution complicates design and increases system volume.
An alternative is to parallel a GaN power HEMT with a device with a lower breakdown voltage, such as a monolithically integrated silicon or SiC p-n junction diode. But such pairings are problematic, entailing intensive research into stress compensation during the growth of GaN epitaxial layers on specially designed substrates. What’s more, there’s the need for additional fabrication steps to form diodes within the substrate and electrically connect diodes with corresponding HEMTs. This adds to complexity and overall cost.
Due to the drawbacks of the two approaches just outlined, a better approach is needed for delivering repetitive non-destructive breakdown behaviour. Rather than pairing the GaN HEMT with other devices or circuits, efforts should be directed at refining this transistor.
Figure 1. The structure and process flow of the proposed p-GaN gate punch-through HEMT (PT-HEMT).
Punch-through gate design
Offering one solution is our team from Peking University. We are pioneers of a novel punch-through concept, based on a standard E-mode p-GaN gate HEMT platform (see Figure 1).
Our device, fabricated on a standard p-GaN gate HEMT epiwafer, delivers E-mode operation. Its uniqueness comes from its combination of: an array of p-GaN islands along the width of the device, providing a control gate; and a thinned p-GaN layer, acting as a punch-through gate (PT-gate), that covers most of the access region. We position the PT-gate edge at 3 μm from the drain terminal.
When the PT-gate is fully depleted under a high drain bias, this leads to a punch-through of the underlying 2DEG channel at a large yet safe off-state drain bias. This results in a non-destructive breakdown. Modulating the length and thickness of the PT-gate layer enables adjustments to the breakdown voltage, to accommodate various voltage ratings.
We fabricated our devices on a 2-inch GaN-on-sapphire wafer featuring a buffer layer, a 200 nm-thick GaN layer, a 15 nm-thick Al0.2Ga0.8N barrier layer, and a 90 nm-thick p-GaN layer. Partial etching of the p-GaN layer forms gate islands, before a second etch defines the PT-gate. On this processed wafer we deposit a 50 nm-thick SiO2 layer by plasma-enhanced CVD at 300 °C. Etching of this SiO2 layer and then depositing a Ti/Al/Ni/Au stack introduces source and drain ohmic contacts, annealed at 810 °C. Fluorine ion implantation provides planar isolation, prior to the deposition of a Ni/Au stack on gate islands, annealed to form an ohmic contact to p-GaN. Another SiO2 layer is then deposited by plasma-enhanced CVD, before contact windows are formed by a dry etch. Finally, a Ti/Au stack is added, to provide metal interconnections and probing pads.
Crucially, this fabrication process is compatible with standard p-GaN gate HEMT technology. Fabrication of the PT-gate structure is easy to realise with an additional p-GaN etching process.
Underlying mechanism
When our device is in its off-state, a high drain bias generates a depletion region within the PT-gate, which is the thinned p-GaN layer. This depletion region expands progressively from the drain side toward the source side, and once the PT-gate is fully depleted, it loses electrostatic control over the underlying 2DEG channel. At this point the 2DEG channel is punched through, resulting in a non-destructive breakdown.
To provide experimental evidence of this mechanism, we have investigated the relationship between the PT-gate depletion voltage and the punch-through breakdown voltage. This involved fabricating a dedicated p-channel JFET to analyse the depletion dynamics of the thinned p-GaN layer. In this configuration, the thinned p-GaN layer serves as the conduction channel, while an ohmic contact to the 2DEG acts as the gate. When we increase the gate-to-source voltage to the threshold voltage, the depletion region expands beyond the length of the p-GaN layer to pinch off the p-channel current path. Measurements show that the threshold voltage increases with the length of p-GaN layer and the thickness of the thinned p-GaN.
We fabricated specific test devices to characterise the punch-through breakdown voltage with different designs, in terms of the length of the p-GaN layer and the thickness of the thinned p-GaN. All devices feature a PT-gate covering the 2DEG channel and a control gate outside the active region. During characterisation at a gate-to-source voltage of 0 V, we observed a sharp rise in current after the drain-to-source voltage reached the punch-through breakdown voltage, signalling the onset of the punch-through effect.
A summary of the relationships between the length of p-GaN layer, and both the PT-gate depletion voltage and the punch-through breakdown voltage, is provided in Figure 2 (b) and (c). Definitive evidence that the full depletion of the PT-gate is the cause of non-destructive breakdown behaviour in PT-HEMTs is provided by the well-matched values for the PT-gate depletion voltage and the punch-through breakdown voltage.
Figure 2. (a) Schematic illustration of the punch-through breakdown mechanism in the PT-HEMT. Summary of the PT-gate depletion voltage (VTC) and punch-through breakdown voltage (VPT) as a function of LP with (b) TP = 20 nm and (c) TP = 33 nm.
Non-destructive breakdown
To underscore the importance of our new design, we have compared the off-state characteristics of our PT-HEMT with a conventional p-GaN gate HEMT (see Figure 3 (a)). Both these devices have a gate-to-drain spacing of 12 μm, and the PT-HEMT has a p-GaN thickness of 33 nm. For the conventional HEMT, catastrophic, destructive breakdown occurs at 1176 V – that’s defined as the voltage where drain current rises sharply. Following this breakdown, the device behaves as a low-resistance resistor, indicating that the breakdown is destructive. In contrast, our PT-HEMT exhibits a stable, non-destructive breakdown behaviour at a clamping voltage of 874 V, offering a built-in safety margin for power systems.
We have investigated the temperature dependence of the punch-through mechanism. Our measurements reveal that the breakdown voltage of our PT-HEMT climbs from 874 V at 25 °C to 992 V at 125 °C (see Figure 3 (b)). Note that this positive temperature coefficient – potentially linked to temperature-dependent trapping and de-trapping processes – is highly desirable for power applications. The primary benefit of a positive temperature coefficient is the promotion of a more uniform current distribution across the device area during breakdown events. In turn, this prevents localised overheating and enhances overall robustness.
For GaN power HEMTs, another critical bottleneck that restricts the application of these devices to higher voltage ratings is a degradation in the dynamic on-resistance. Due to this concern, we have investigated if this is an issue in our devices (see Figure 3 (c)).
Figure 3. (a) Off-state performance of the conventional HEMT and PT-HEMT with an LGD of 12 µm. The breakdown in conventional HEMTs is destructive, while in PT-HEMTs it is non-destructive. (b) Temperature-dependent off-state performance of PT-HEMTs. (c) Dynamic RON characteristics of the conventional HEMT and PT-HEMT.
The good news is that while conventional HEMTs suffer from severe dynamic degradation in on-resistance, due to charge trapping, our PT-HEMTs maintain exceptional stability. We attribute this superiority to the dual role of the PT-gate: first, surface trapping is effectively screened by mobile holes within the PT-gate; and second, buffer trapping is significantly suppressed by hole injection from the PT-gate into the underlying layers. Consequently, the PT-HEMT achieves a remarkably low ratio between the dynamic and static on-resistance: it is less than 1.2, even after high-voltage stress.
Thanks to the incorporation of a punch-through path, our design effectively overcomes the inherent absence of avalanche breakdown in the GaN HEMT. By equipping our devices with a non-destructive breakdown capability, alongside a low dynamic on-resistance degradation, we have positioned them as very compelling candidates for hardening power systems in harsh operating conditions.
To demonstrate the non-destructive breakdown behaviour of our PT-HEMT more intuitively, we have undertaken rigorous repetitive breakdown characterisation, which includes current-driven breakdown measurements (see Figure 4 (a)). During the test, we limited the maximum current to 100 µA mm-1 to prevent overheating of our devices. We set the gate-to-source voltage to 0 V, and employed a current source to force a drain current through our device. Encouragingly, our PT-HEMT successfully sustained over 100 non-destructive breakdown cycles, while clamping the drain-source voltage at a punch-through voltage of approximately 870 V.
We have recorded the static and dynamic performance of our PT-HEMT before and after 100 cycles of punch-through breakdown (see Figures 4 (b) and (c)). This device exhibits a stable threshold voltage and subthreshold swing. Crucially, even after repetitive high-voltage stress, our PT-HEMT maintains a ratio for dynamic-to-static on-resistance of just 1.18, at a drain stress voltage of 650 V. This result shows that our PT-HEMTs have an inherent capability to handle transient overvoltage spikes in high-power switching applications.
Figure 4. (a) Current-driven breakdown characteristics of a PT-HEMT with an LGD of 12 µm, demonstrating 100 cycles of non-destructive breakdown with stable breakdown voltages around 870 V. (b) Transfer curves and (c) dynamic RON/static RON ratio of a PT-HEMT before and after 100 cycles of non-destructive breakdown.
There is good reason to believe that our PT-HEMT will support the growth of applications that GaN power electronics can serve. One of its key metrics is its flexibility, with modifications to the length and thickness of the PT-gate layer enabling the device to cater for different voltage requirements. As our novel transistors are inherently suitable for handling transient overvoltage spikes in high-power switching applications, they promise to deliver a step-change in transient-overvoltage robustness in high-voltage GaN technology.
