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Unipolar Transistors Open III-V Logic Prospects

A Yale professor has developed an NMOS-based technology that avoids the problems of low hole mobility, and high power consumptions at standby that dogged previous incarnations.

Smaller and faster logic circuits could arise from a transistor concept proposed by a US academic "“ with compound semiconductor devices set to be the greatest beneficiaries.

Tso-Ping Ma proposes logic transistors that avoid a key downfall of the NMOSFET and PMOSFET pairing used in conventional CMOS. That downfall arises because n-channel carriers (electrons) move much faster than those in the p-channel (holes), making the performance of the PMOSFET a limiting factor.

The Yale electrical engineering professor has now invented a system that consists of two NMOSFETs, which he calls the Unipolar Complementary Field-Effect Transistor (UCFET) concept. “This approach removes a huge road block that has hindered the development of III-V logic circuits," Ma told compoundsemiconductor.net.

Ma reminded the 5th International Symposium on Advanced Gate Stack Technology in Austin, Texas, at the end of September that silicon suffers from an electron:hole mobility ratio of 2.8. In GaAs this ratio is 9.2 and in InAs it is greater than 80, meaning investigations into the use of III-Vs for logic by Intel and others have been limited to the n-channel, with germanium widely expected to take the p-channel role.

Poor p-channel performance is usually compensated by making it wider than the n-channel, in the same ratio as that between carrier mobilities. UCFETs avoid this miniaturization-hampering scaling approach and appear to provide a way to attack Moore s Law from both the size and performance fronts.

All-NMOS logic dates back to pre-CMOS times, but inverters made in this way dissipated power even when the circuit sat idle. CMOS logic became the dominant technology that we know today because it minimizes standby power consumption.

To avoid this pitfall, Ma s proof-of-concept silicon-on-insulator inverter circuit uses insulating regions to carefully control electron flow, giving one channel a positive threshold voltage, and the other a negative threshold voltage. This complementary nature thus distinguishes the UCFET from conventional NMOS logic.

Ma is now doing more simulations, developing more basic logic circuits and working on process designs. Yale is also seeking collaborators to jointly fabricate demonstration devices, including from III-V materials. He expects that more advanced circuits will quickly come to the fore to exploit the UCFET concept.

“This design, although easy to sketch to demonstrate the principle, is not ideal due to the possibility of large capacitance associated with the back gate," Ma said. “A 3-D structure, such as FinFETs, double gate or tri-gate FETs should be better in terms of the gate capacitance consideration."

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