+44 (0)24 7671 8970
More publications     •     Advertise with us     •     Contact us
 
Loading...
News Article

Debut for double-quantum-well tunnel FET

Novel tunnel FET targets low power and radio frequency applications



Engineers from MIT have fabricated a double quantum well FET (a). Cross-sectional tunnelling electron microscopy provides images of the tunnelling junction and gate stack in the gated region (b), and the edge of the InGaAs air bridge (c). A top view of the air-bridge, after suspension, is provided by a scanning tunnelling microscope (d).


Engineers from MIT are claiming to have fabricated the first tunnel FET with a double quantum well InGaAs/GaAsSb structure.

Additional accomplishments for this team, which work at the Microsystems Technology Laboratory, are a first demonstration of area-dependent drive current for this class of device and the realisation of backward-diode operation characteristics (backward diodes

deliver their highest current when reverse biased, due to tunnelling of carriers).

This team’s novel FET is a promising device for two types of application: It has the potential to deliver a very low sub-threshold swing – a measure of the change in voltage needed to increase the drive current by an order of magnitude – making it attractive for low power applications; and as a backward diode, it could find deployment in radio frequency applications for mixing and detection.

One of the team’s motivations for developing its double quantum well TFET has been to expand the drive current range capable of delivering a low sub-threshold swing. Previous forms of TFET have demonstrated a sub-60 mV/decade sub-threshold swing, but only at low drive currents.

In 2011, Sapan Agarwal and Eli Yablonovitch from the University of California, Berkley, unveiled the results of theoretical investigations, which suggested that density-of-state switching is capable of realising a steep sub-threshold swing over a wide range of drive currents. In order to produce this form of switching, the TFET must feature two quantum wells overlapping in the confinement direction.

The MIT device exhibits this trait, with wells formed by an 18-nm thick p-type GaAs0.5Sb0.5 layer doped with beryllium to a concentration of 1019 cm-3, and a 15 nm-thick n-type In0.53Ga0.47As layer doped with silicon to a concentration of 1017 cm-3. These epilayers were deposited onto a semi-insulating InP substrate by MBE (see Figure).

Device fabrication involved: patterning with e-beam lithography; the addition of a HfO2 gate dielectric, which is

5.3 nm-thick, by atomic layer deposition; and removal of GaAsSb to suspend an InGaAs air bridge via a highly selective wet etch. Depositing a layer of Al2O3 passivated the device.

Measurements by the team show that the current delivered by their TFET is proportional to its gate area. Four devices were used to determine this, with gate areas ranging from just above 10 mm2 to almost 90 mm2.

A weakness of the device is its high sub-threshold swing: its minimum value is 140 mV/decade, and it has an effective value of 220 mV/decade over 20 nA to 2 µA.

The engineers from MIT believe that one of the causes of the high sub-threshold swing is the high off-current. This may originate from leakage through the 30 nm-thick InP buffer layer, and could be addressed by undercutting the InP layer under the drain current.

Another reason for the high sub-threshold swing is the high density of interface traps, which are located in the InGaAs conduction band at the HfO2/InGaAs interface.

According to capaitance-volatge measurements, the minimum value for the denisty of interface traps is 2 x 1012 cm-2 eV-1.

“The density of interface traps is mainly due to the dangling bonds on the InGaAs surface, prior to dielectric deposition,” explains Tao Yu from MIT, who believes that these traps might be minimised with a passivation step involving chemical methods or plasma treatment.

Measurements of the gated-diode nature of the TFET reveal that it exhibits tuneable backward diode behaviour. The gate bias can be adjusted to optimise minimum noise or high sensitivity.

“We have not yet done a deeper study on the actual RF performance of the device, but according to previous studies on backward diodes, the RF application of the device should be promising after calibration and optimisation,” says Yu.

Other plans for the team are to suppress the interface trap density, cut leakage and improve sub-threshold swing through optimisation of the gate dielectric and device architecture.

T. Yu et. al.

IEEE Electron Dev. Lett. 34 1503 (2013)

×
Search the news archive

To close this popup you can press escape or click the close icon.
×
Logo
×
Register - Step 1

You may choose to subscribe to the Compound Semiconductor Magazine, the Compound Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: