Technical Insight
IEDM showcases compound semiconductor successes
III-V devices deliver record on-currents, unprecedented gain at terahertz frequencies and far lower power-switching losses
BY RICHARD STEVENSON
For more than 50 years, the International Electron Devices Meeting (IEDM) has been highlighting advances in silicon technologies. More recently, however, this conference has also been showcasing important breakthroughs in compound semiconductor technologies. And at the most recent meeting "“ held in San Francisco from 3-7 December, 2016 "“ the coverage of innovations in III-Vs reached an all time high, with reports of success including: record-breaking currents in III-V MOSFETs; a new benchmarks for gain in InP HEMT ICs at 1 THz; unprecedented breakdown voltages and reverse leakage currents in a GaN rectifier; and the development of a novel, normally-off vertical GaN transistor and a current-collapse-free GaN gate injection transistor.
Advances in the performance of III-V MOSFETs, which promise to maintain the march of Moore's law, have been a common theme at IEDM gatherings during the last decade. And the last meeting continued this trend, with a presentation from Cezar Zota and co-workers from Lund University, Sweden detailing the breaking of the record for the on-current in any III-V or silicon MOSFET (see Figure 1). The team's InGaAs tri-gate MOSFET produces 650 mA/mm at a supply voltage of just 0.5 V.
Increasing the on-current is a significant achievement. "If it is higher than the levels required for circuit operation, then the supply voltage can be reduced so that the on-current is reduced to just the required level," explains Zota. As overall power consumption is proportional to the square of the supply voltage, the power required to operate the circuit falls dramatically "“ and if the circuit is used in a mobile device, this leads to a longer battery life. Another benefit of trimming the supply voltage with node size is that it can prevent an escalation of the chip power density.
Advances in the performance of III-V MOSFETs, which promise to maintain the march of Moore's law, have been a common theme at IEDM gatherings during the last decade. And the last meeting continued this trend, with a presentation from Cezar Zota and co-workers from Lund University, Sweden detailing the breaking of the record for the on-current in any III-V or silicon MOSFET (see Figure 1). The team's InGaAs tri-gate MOSFET produces 650 mA/mm at a supply voltage of just 0.5 V.
Increasing the on-current is a significant achievement. "If it is higher than the levels required for circuit operation, then the supply voltage can be reduced so that the on-current is reduced to just the required level," explains Zota. As overall power consumption is proportional to the square of the supply voltage, the power required to operate the circuit falls dramatically "“ and if the circuit is used in a mobile device, this leads to a longer battery life. Another benefit of trimming the supply voltage with node size is that it can prevent an escalation of the chip power density.
Figure 1. The InGaAs tri-gate MOSFET produced by researchers at Lund University is claimed to deliver a record on-current for any silicon and III-V MOSFET.
The team from Lund University fabricate their devices by depositing an In0.85Ga0.15As film on an InP substrate by MOCVD, and then defining the nanowires with a hydrogen silsesquioxane growth mask and a digital etch. Evaporation and lift-off create source and drain contacts, and the gate is formed by adding Al2O3 and HfO2 and a Ni/Pd/Au gate metal.
The team from Lund University fabricate their devices by depositing an In0.85Ga0.15As film on an InP substrate by MOCVD, and then defining the nanowires with a hydrogen silsesquioxane growth mask and a digital etch. Evaporation and lift-off create source and drain contacts, and the gate is formed by adding Al2O3 and HfO2 and a Ni/Pd/Au gate metal.
Transistors are produced with a variety of sizes, because this can determine the limit of the material quality of InGaAs with reduced nanowire dimensions. The smallest devices are 25 nm wide, and have an 8 nm height. "Since scattering is dominated by the 8 nanometre dimension, this would correspond to the 10 nanometre node," says Zota. "However, the overall dimensions in our nanowires are not the same as for the fins in the 10 nanometre node "“ therefore, the comparison must be made carefully."
If these devices are to be introduced in next-generation ICs, their substrate must switch from InP to silicon. There are plenty of options for moving to this foundation, argues Zota, pointing out that this could be accomplished by: wafer bonding techniques; selective growth, such as the template-assisted growth scheme pioneered by IBM; and the use of buffer layers, which are now capable of combining thicknesses below 100 nm with low defect densities.
As the width of the devices is scaled down from a planar architecture to 25 nm, the transconductance maximum increases to 3.3 mS/µm. This is attributed to an increase in indium richness in the nanowire and a beneficial change in the distribution of interface states.
Another advantage that stems from scaling is a reduction in sub-threshold swing: when the nanowire width shrinks from 1 µm to 25 nm, this falls from 100 mV/dec to 66 mV/dec. Short-channel effects are also addressed, and can be further reduced by introducing either a wider bandgap substrate, or a III-V-on-insulator structure.
Meanwhile, experiments with oxide scaling shows that a reduction in the equivalent oxide thickness (EOT) from 1.4 nm to 1 nm can reduce the sub-threshold swing from 81 mV/dec to 75 mV/dec. And additional improvement is possible, says Zota, arguing that other groups have realised an EOT of 0.7 nm "“ and he and his co-workers should be able to reproduce this. Further gains could be made by replacing the "sub-optimal" bilayer Al2O3/HfO2 stack, which has a low k-value for the Al2O3, with a single layer of HfO2 or ZrO2.
Strength of the InGaAs tri-gate MOSFET produced by researchers at Lund University include a sub-threshold swing that can be as low as 66 mV/decade and a transconductance of 3 mS/µm.
The team is currently developing an MOCVD selective-growth technique for realising high-aspect-ratio nanowires. Higher current-densities per chip-area could result from this approach, which involves optimisation of growth conditions and the substrate surface orientation to promote the growth of vertical side walls. "This could allow us to obtain industry-relevant fin dimensions, while maintaining our etch-free fin formation scheme and high electron mobility," argues Zota.
The team is currently developing an MOCVD selective-growth technique for realising high-aspect-ratio nanowires. Higher current-densities per chip-area could result from this approach, which involves optimisation of growth conditions and the substrate surface orientation to promote the growth of vertical side walls. "This could allow us to obtain industry-relevant fin dimensions, while maintaining our etch-free fin formation scheme and high electron mobility," argues Zota.
Terahertz gain
At Northrop Grumman researchers are developing high-frequency InP transistors for terahertz applications, and at IEDM Bill Deal revealed that they had just hit another milestone: the first demonstration of transistor amplifier gain at or above 1.0 THz. The team's ten-stage amplifier, made from 8 µm transistors, produces a gain of 10 dB at 1.0 THz.
At Northrop Grumman researchers are developing high-frequency InP transistors for terahertz applications, and at IEDM Bill Deal revealed that they had just hit another milestone: the first demonstration of transistor amplifier gain at or above 1.0 THz. The team's ten-stage amplifier, made from 8 µm transistors, produces a gain of 10 dB at 1.0 THz.
Deal told Compound Semiconductor that the transistor technology is already being used for several NASA technology projects, and is expected to be commercialized in the next three-to-five years.
Radio astronomy, atmospheric sensing, and the study of material properties could all benefit from the efforts at Northrop Grumman, because all these applications involve measuring the absorption of radiation at terahertz frequencies. "Having amplifiers at these frequencies may enable new types of radiometric measurements and further our understanding of the physical world," argues Deal.
The team's InP transistor amplifiers also promise to slash the size, weight and power consumption of terahertz receivers. Today, these receivers employ diode-based technologies, and operate at low DC efficiencies. Deal claims that the direct power amplification provided by InP transistors can improve radiometric receiver DC efficiency by more than ten times, and ultimately enable new types of science missions.
A key technology in the InP transistors is a 25 nm, T-shaped gate that is defined by 100 kV, electron-beam lithography. After forming the gate, etching creates a gate recess, with the metal-semiconductor interface located less than 2 nm above the silicon doping plane. Following the gate recess process, a Ti/Pt/Au-based gate metal is evaporated by electron-beam evaporation. To improve reliability and robustness, a SiN film is added to passivate the devices.
Recently, the team at Northrop Grumman have been working on packaging their devices. This is challenging, because at terahertz frequencies it is not easy to couple the radiation between the waveguide and IC. To address this issue, the device is engineered so that an electromagnetic transition occurs on the IC. Dipole antennae are placed on the left and right side of the chip, which has had material removed from its corners.
The team's terahertz transistor is currently being investigated for its suitability for atmospheric science. This is taking place through a variety of NASA-funded research projects, which include the development of an instrument that could be mounted on a satellite to measure tropospheric water and cloud ice.
Fantastic field rings
To improve the performance of vertical GaN diodes for power applications, a partnership between MIT and the Singapore-MIT Alliance for Research and Technology has been developing a novel device with implanted field rings (see Figure 2). Detailing their GaN vertical Schottky rectifier at IEDM, Yuhao Zhang from MIT explained that their modifications to the device slashed the leakage current by a factor of more than 104 and increased the blocking voltage from 400 V to 700 V. The turn-on voltage is retained at 0.8 V "“ in comparison, it is typically more than 3 V for lateral p-n GaN diodes, which are renowned for their high blocking voltages and low leakage currents.
According to Zhang, the key to combining Schottky-like forward characteristics, such as the low turn-on voltage, with the high blocking voltages and low off-state currents that are associated with devices that feature a p-n junction, is to move the peak electric field away from the Schottky contact. "As p-type ion implantation, or selective epitaxial growth, is still very challenging for GaN devices, we designed this trench-based MIS structure with field rings, to move the high electric field without the need for p-GaN."
Figure 2. Trenches and field rings enable the rectifier produced by MIT and the Singapore-MIT Alliance for Research and Technology to combine a high breakdown voltage with a very low reverse leakage current.
The device that results could provide high-frequency power-switching at 600 V, making it a promising candidate for deployment in electric vehicles, data centres and various power systems.
Fabrication of the device began by growing, by MOCVD, a 7 mm-thick layer of n-type GaN on a free-standing substrate. Multiple trenches with a depth of 2 mm were formed, before adding a metal-insulator-semiconductor (MIS) film stack to the trench bottoms and sidewalls. Inserting implanted field rings below the trench bottom followed, along with the addition of a Schottky contact on the top GaN surface.
Simulations with the commercial software Silvaco Atlas provided a great insight into the benefits of the novel architecture. With this particular design, the electric field at the Schottky interface is greatly reduced, leading to an exponential decrease in the leakage current from the Schottky contact; the peak of the electric field is shifted from the upper surface into the bulk GaN; the field rings smooth the electric field stress in the dielectrics near the trench corners of this device; and adjustments to the mesa width alter the level of electric-field shielding of the Schottky junction, and lower the electric field near the field rings (see Figure 3).
Figure 3. Improvements in the performance of a trench MIS barrier Schottky rectifier with implanted field rings stem from modifications to the electric field profile. These changes can be assessed with the commercial software Silvaco Atlas.
To verify these benefits, Zhang and co-workers fabricated three different structures: a Schottky barrier diode, a trench MIS barrier Schottky rectifier, and a trench MIS barrier Schottky rectifier with implanted field rings. The benefits of the trench MIS barrier Schottky rectifier over the Schottky barrier diode are an increase in blocking voltage from 410 V to 510 V and a fall in leakage current by two orders of magnitude. The introduction of field rings delivers a further hike in blocking voltage to 700 V and an additional reduction in the leakage current by two orders of magnitude. The only downsides of the field rings are a slight reduction in turn-on speed and an increase in turn-on voltage from 0.7 V to 0.8 V.
The field-ring, trench MIS barrier Schottky rectifier is also claimed to be the first high-voltage GaN vertical Schottky barrier diode capable of operating above 200 °C, making it suitable for operation in some extreme environments. "The capability of operation at higher temperatures would typically enable a higher power output," says Zhang.
One of the next goals for the team is to improve the performance of the rectifier so that its breakdown voltage increases to more than 1200 V. "At the same time, we will utilise this technique to make normally off GaN vertical transistors."
Superior switching
A device that already delivers normally off operation is the GaN gate injected transistor (GIT), and at IEDM Hiroyuki Handa from Panasonic revealed how to slash its switching losses. This device, which is a promising candidate for deployment in compact inverters and converters in consumer products, is usually grown on silicon substrates. However, turning to GaN delivers a three-fold improvement in a key figure of merit for switching efficiency.
The GIT, which operates by injecting holes from the p-type gate over an AlGaN/GaN heterojunction to increase the drain current and maintain normally off operation (see Figure 4), is already being sampled in its GaN-on-silicon form.
Figure 4. The GaN gate injection transistor developed by Panasonic features a recessed gate structure that reduces the series resistance.
Recently, advances in switching technology have led to the introduction of so-called soft switching, which eliminates turn-on switching loss by eliminating overlap between the current and voltage at turn-on (see Figure 5). There is still a loss "“ but it occurs at turn-off, due to an overlap of current and voltage. Consequently, the key criteria for the GIT is how fast it can be turned off, as this minimises switching loss and allows the use of higher frequencies "“ and ultimately opens the door to trimming the size, cost and weight of other components in the circuits.
Figure 5. With a typical zero volt switching approach, only turn-off switching causes a switching loss.
Growing the GIT on a GaN substrate with a thick buffer layer increases its switching capability by cutting the output charge, reducing the on-resistance, and enabling current-collapse-free operation up to 1 kV.
To determine the level of improvement wrought with a thick buffer on a native substrate, Handa and co-workers produced a pair of devices: a GIT with a 5 µm GaN buffer, grown on a silicon substrate (this is the maximum possible thickness, due to thermal and lattice mismatch); and a variant that is identical, except for a 16 µm GaN buffer and a GaN substrate. Note that simulations suggest that the output charge reduces with increasing buffer thickness, but saturates at a thickness of 15 µm.
Measurements on both types of device reveal that using a thicker buffer, and switching from a silicon substrate to GaN, drives down a key figure of merit "“ the product of on-resistance and output charge "“ from 2745 mΩ nC to 940 mΩ" nC. Additional improvements include a reduction in the switching rate from 140 V/ns to 285 V/ns, a 60 percent increase in the drain current and a hike in the breakdown voltage from 1050 V to 2800 V.
Handa admits that one of the downsides of the superior device is a production cost that is "currently very high", due to the use of native GaN substrates and thick buffer layers. But it could come down by increasing the wafer diameter and the growth rates.
"The next plans are reliability tests, to compare with GaN-on-silicon GITs," says Handa.
Semi-polar gates in GaN
One of Handa's colleagues at Panasonic, Daisuke Shibata, also presented pioneering work at IEDM "“ in this case, the development of a 1.7 kV, normally off, vertical GaN transistor that is grown on a native substrate and features a semi-polar gate structure (see Figure 6). This device is claimed to be the first vertical GaN transistor to offer stable gate performance.
"Our re-grown p-Gan/AlGaN/GaN semi-polar gate can be applied to other vertical devices," says Shibata, explaining that it could not only equip them with a more stable gate, but also a higher threshold voltage "“ it is 2.5 V in their device. "A higher threshold voltage is strongly desired to prevent false operation caused by circuit noise."
Figure 6. The threshold voltage of the vertical GaN transistor produced by Panasonic increases with the tilt angle, q.
The 1.7 kV transistor will target power switching systems. Engineers of these systems are currently evaluating lateral AlGaN/GaN transistors that are formed on silicon substrates and have blocking voltages of up to 600 V. Shibata says that the performance of these devices, including their reliability, is good enough for practical use. However, they are held back by a limit to the total output power of several kW. The lateral geometry hampers increases to the current and the voltage, which is limited to 1 kV, due to restraints on the thickness of GaN layers grown on silicon.
Shibata and co-workers are by no means the first to turn to vertical transistors to overcome the limitations of the lateral device. But in general, efforts have been hampered by low threshold voltages, and low stability of the gate, due to instability between an oxide and GaN. With the team from Panasonic, both of these issues have been addressed.
Success results from the design of the device, which features the growth of three layers - a p-GaN gate, AlGaN and GaN "“ on a V-grooved surface that is formed in p-GaN well and n-GaN drift layers (see Figure 7).
Tilting the layers delivers a hike in threshold voltage. As the angle of the tilt compared with the plane of the wafer (shown as 0 in Figure 6) increases from 0° to 90°, calculations suggest an increase in threshold voltage from just over 1 V to almost 4 V. Experiments confirm the extent of the benefit, with a threshold voltage on the c-plane surface of just 1 V, which is 1.5 V less than the device incorporating a semi-polar gate.
Figure 7. A cross-sectional scanning electron microscopy image of Panasonic's vertical GaN transistor, which is claimed to feature the first stable gate for this class of device.
Another feature of the transistor of Shibata and co-workers is the inserted carbon-doped GaN layer. This suppresses the punch-through current and enables a hike in breakdown voltage from 580 V to 1.7 kV.
This device offers fast switching at 400 V and currents of up to 15 A. "Our next plan is realizing higher current operation in vertical GaN transistors," says Shibata.
During the next 12 months, breakthroughs in GaN transistors and other III-Vs will occur at Panasonic and elsewhere. Some of the most significant of these will be reported at IEDM 2017, which will be held in San Francisco, and is tipped to feature an ever greater coverage of compound semiconductor devices.
