Uniting high-mobility transistors on silicon

Selective epitaxy can scale field-effect transistors featuring InGaAs and SiGe channels to small enough dimensions for next-generation CMOS

BY LUKAS CZORNOMAZ FROM IBM

There are three key components in today's information technology. One, involving smartphones and Internet-of-Things technologies, is a dense, mobile network of nodes for collecting and pre-processing data. Another is the efficient, broadband infrastructure that transmits the data. And the third, coined Cloud Infrastructure, is the de-materialized space for high-performance data storage and processing.

For the electronic devices found at the beginning and at the end of this chain, it is becoming tougher than ever to reduce power while increasing performance. Here, compromise is the name of the game, commonly seen in the reduced battery life of smartphones and the tremendous challenges for cooling datacenters.

If we rewind the clocks to the first few decades of the silicon industry, the situation was markedly different. Back then geometrical scaling delivered the desired gains in performance and reduction in power with every new technology node. But now new materials are needed to maintain progress. This began with the introduction of high-k gate dielectrics in 2007 at the 45 nm node. By replacing SiO₂ with HfO₂, designers have been able to maintain the supply voltage while keeping the parasitic power associated with the gate leakage at acceptably low levels.

Figure 1. A top-view, scanning electron microscopy image of an InGaAs/SiGe 6T-SRAM array on silicon with a cell size of 0.4 µm². This image is taken after completion of front-end-of-the-line fabrication.

Nowadays, meeting the targets in power consumption call for a substantial reduction in the supply voltage. A promising approach for delivering the next revolution in the semiconductor industry is to switch from silicon to compound semiconductor channel materials. This move increases carrier mobility, allowing for a trimming of power consumption while increasing performance. Success on both these fronts is possible, because the supply voltage can be reduced while maintaining a large drain current, and therefore a high performance level.

The increases in mobility with this radical move are substantial. For the benchmark material, silicon, electron and hole mobility is typically 1400 cm² V^-1 s^-1 and 450 cm² V^-1 s^-1, respectively. In comparison, electron mobility in InGaAs is more than six times higher, exceeding 10000 cm² V^-1 s^-1, and hole mobility in germanium is four times higher, and can be as high as 1900 cm² V^-1 s^-1.

Thanks to these far higher values, an advanced CMOS technology can propel the power-performance trade-off to a level that conventional silicon CMOS can only reach after two-to-three scaling nodes. However, optimizing electron and hole transport separately implies to have two different compounds (InGaAs and SiGe) co-integrated on the same chip, which is a major challenge

Up until now, despite much effort, the industry has not been able to demonstrate a suitable co-integration technology. It is a tall order, requiring the fulfilment of many criteria. The technology must be suitable for silicon substrates and it has to be compatible with thestandard CMOS design environment. What's more, it must simultaneously allow the growth of defect-free InGaAs, the fabrication of high-performance InGaAs FETs, and the co-processing of these transistors with SiGe devices.

Figure 2. Etching the SiGe-on-insulator wafer (a) defines the pFET active region and an opening for the silicon seed (b). Sacrificial material is then added (c), before capping with an oxide and adding an opening to this layer. Sacrificial material is removed (d), before InGaAs grows from the seed (e) through the neck (f) to fill the cavity (g). The oxide cap is removed (h), before forming a nFET active region and ultimately InGaAs nFETs and SiGe pFETs (j). A simplified process using a common high-/metal gate has been pursued by IBM Zurich (i').

At IBM Research in Zurich, our team has more than ten years of expertise on this topic. This expertise has been built over time through many achievements including: the development of unique methodologies to integrate InGaAs with large-size, bulk silicon substrates; the building of CMOS-compatible transistors and optimization of their performance; and the demonstration of hybrid CMOS circuits, including the evaluation of their impact on future CMOS technology nodes.

Our latest and major highlight has been the first demonstration of an InGaAs/SiGe CMOS technology on a silicon substrate, using fabrication processes suitable for high-volume manufacturing on 300 mm wafers. This recent work breaks new ground by demonstrating basic building blocks of digital circuits at relevant dimensions. It is a major milestone towards a manufacturable, hybrid InGaAs/SiGe CMOS technology, which is the main path for enabling further improvement in the power/performance tradeoff for digital technologies beyond the 7 nm node.

Based on selective epitaxy, our novel approach has yielded functional inverters and dense arrays of 6T-SRAMs (see Figure 1).

Production of these circuits began by integrating InGaAs and SiGe crystals on silicon substrates with a novel, patented, selective growth process "“ it is based on MOCVD, and forms thin InGaAs platelets in empty oxide cavities (see Figure 2). Note that although this circuit integration has been demonstrated on a SiGe-on-insulator wafer, it can be readily implemented on bulk silicon or on silicon-on-insulator.

Processing began with dry etching, to form pFET active regions that can be either mesas or fins. We then formed empty SiO₂ cavities. They offer access to the silicon substrate, which acts as a crystalline seed. Following this, we refilled the empty cavities using an InGaAs epitaxy step. During this, the growth direction changed from vertical to lateral. Switching the growth direction is advantageous, as it allows the handling of defect filtering with a minimal area penalty, while defining nFET active regions by the lateral growth direction.

A noteworthy merit of this approach is that it is well-suited to the high density requirements for CMOS technology. Referred to as confined epitaxial lateral overgrowth, it belongs to a family of template-assisted selective epitaxy techniques.

Once the InGaAs areas have been integrated next to the SiGe areas on the silicon substrate, FinFETs are fabricated. For this, we use a CMOS-compatible self-aligned flow that enables aggressive scaling of transistor density. InGaAs fins are defined by dry etching with an inductively coupled plasma, before plasma-enhanced, atomic-layer deposition adds a high-k and metal-gate stack of Al₂O₃, HfO₂ and TiN. Once the gate has been dry etched, SiN sidewall spacers are formed, before selective n⁺ InGaAs raised source and drain regions are grown epitaxially. Standard tungsten-plug contacts are then realized.

One of the significant challenges that we have faced is the need to develop new fabrication processes to accommodate the very different process requirements of InGaAs and SiGe. That's because typical wet clean and dry etching processes for SiGe are not selective to InGaAs; different surface preparations are needed for the high-k gate stacks for InGaAs and SiGe; InGaAs and SiGe require different source and drain materials; and both materials require very different processing thermal budgets. Addressing these requirements implies numerous key findings discovered over years of experimentation, converging into the establishment a novel process flow.

Another key to our success has been the development of a design-technology co-optimization algorithm that is able to adapt standard IP blocks to the novel III-V selective growth in oxide cavities. Armed with this, we have optimized the placement of seeds and cavity openings.

Figure 3. The cross-section through the gate of a CMOS inverter of a 6T-SRAM cell, where SiGe and InGaAs channels are integrated side by side on a silicon substrate. Separation between the two high-mobility channels is as small as 25 nm.

We used this algorithm for the fabrication of dense 6T-SRAM arrays with a "˜thin-cell' configuration. Our physical demonstrators have a cell size below 0.45 µm². Even smaller values should be possible, as our scalability studies show that our technology is compatible with 7 nm node ground rules.

Our demonstration of scaled InGaAs/SiGe hybrid CMOS circuits has profound consequences for manufacturing technologies. It breaks the conventional wisdom that hybrid InGaAs/SiGe CMOS technology, although being widely acknowledged as the ideal option, is intrinsically limited by engineering bottlenecks, and is therefore unlikely to be commercialized.

Thanks to our efforts, it is now possible to merge processes, metrology, and practices for materials as different as silicon, III-Vs and IV-IVs into a single processing environment. This is not only great news for the future of digital applications "“ it also opens the door to the development of fabs designed for system-on-chip circuits, tightly integrating logic with other technologies such as wireless, power and optical technologies.