3D integration unites InP, GaN and silicon CMOS

Devices in multi-material stacks deliver uncompromised performance, thanks to active substrates, wafer bonding and thermal vias by Andrew Carter and Miguel Urteaga from Teledyne Scientific and Imaging

Compared with silicon-based technologies, devices made with III-Vs offer superior high-frequency performance and better power handling characteristics. However, that's not to say that silicon does not have a role to play. Electronic platforms made from III-Vs lack integrated low-power digital logic, so when they are used to make complex mixed-signal III-V-based systems, they have to interface with silicon CMOS at some level.

If these two material systems are united through intimate heterogeneous integration, this can unlock the door to new classes of microsystems that combine the performance of III-V transistors with the vast IP and manufacturing resources of CMOS. One of the key challenges is to ensure that the heterogeneous integration process does not impair the intrinsic performance of the III-V devices.



Figure 1. There are various options for realising the heterogeneous integration of compound semiconductors.

This pitfall can be avoided through the epitaxial growth of all technologies on a common substrate. Another advantage with this approach is that the devices can then share a common wiring environment. However, the host substrate is costly; and there is the potential for poor device thermal management, due to thick epitaxial buffer layers.

A variation that may address this weakness is the use of an interposer that is also a common active device substrate, such as silicon CMOS. With this approach, some of the interposer cost may be deferred, because it is pre-populated with a technology. Another merit is the dense wiring environment. However, both these benefits can be overshadowed by interchip parasitic losses, which can prevent the system from accessing each technology's intrinsic performance.

There are many different approaches to realising the heterogeneous integration of compound semiconductors and silicon (see Figure 1 for an overview). One option is to simply tile devices made from different materials onto an interposer. With this scheme, known as 2.5D integration, all the materials must form suitable mechanical and electrical interfaces. In general, this is not too tricky, thanks to technologies such as bump bonding and thermocompression bonding. However, the underlying interposer can be prohibitively expensive if the wiring density is too high.


Figure 2. Silicon/InP wafer stacking: schematic cross-section of the technology, and a FIB/SEM cross-section of the completed process.


At Teledyne Scientific and Imaging, we have recently shown that the latter issue is not insurmountable. Using hybrid fusion wafer bonding for electrical interconnection, we form stacks that integrate silicon CMOS with InP and GaN technologies. These stacks feature a high thermal conductivity SiC substrate to improve heat management.

Our three-technology stack combines silicon CMOS with InP BiFETs (HBTs and HEMTs on the same substrate) and GaN HEMTs. Virtues of our technology include minimal inter-technology electrical parasitics and adequate heatsinking for all types of device. At the top of our three-technology stack sits silicon CMOS. This is populated with lower power devices, so minimal heatsinking is required. Below this is the InP device technology, with the InP substrate thinned to 10 μm and bonded face-up to a GaN-on-SiC substrate, which sits at the bottom of the stack to ensure optimal thermal dissipation.

We use Tessera Direct Bond Interconnect (DBI) technology to adhere one material system to another. This approach employs copper vias embedded in a dielectric "“ in this case silicon dioxide "“ and electrical contacts between each substrate, which is aligned to another in either a face-to-face or back-to-face orientation. The pitch for the heterogeneous interconnect via is just 5 μm, so for a chip size of 1 cm², it is possible to have as many as 4 million interconnects. To connect InP to GaN, a tungsten through-substrate-via is formed in InP, and a Direct Bond Interconnect is formed on the back of the thinned InP and the top of a GaN-on-SiC substrate.

Our efforts at developing our triple-stack technology have been divided into two separate but complementary directions: silicon/InP face-to-face bonding, and InP/GaN back-to-face bonding.

InP and silicon CMOS

The face-to-face bonding of silicon and InP enables a form of 3D heterogeneous integration that offers a significant benefit in space-constrained microsystems. Consider, for example, RF beamformer ICs currently in use for radar and high-data-rate communications systems. They consist of an array of gain- and phase-controlled receiver and transmitter channels. By controlling the gain and phase of each channel, it is possible to steer the electronic beam of the major lobe of the beamformer's radiation pattern. To generate the largest scan angle, all the transmitter/receiver antennae are placed on a grid and spaced apart by a distance equal to half the free-space wavelength of the centre frequency of the beamformer. With these RF systems, the trend is to move to higher frequencies, so antennae must be placed closer together. One consequence is that system packaging constraints come into play. That's not a major issue for our technology, however, because our form of 3D integration brings silicon control logic in close proximity to the InP, and can realise ideal grid spacing at millimetre-wave frequencies.


Figure 3. InP/silicon Q-band receiver and transceiver channel RF gains over all states for a fixed phase state.



A key building block for our beamformers operating at millimetre-wave frequencies is our 250 nm InP HBT technology. These devices, which have a 250 nm emitter width, combine maximum values for ft and fmax of 360 GHz and 700 GHz, respectively, with a common-emitter breakdown voltage of 4.5 V.

We have also developed an InP BiFET process, with InP/InGaAs HBTs and InGaAs HEMTs co-planar on the same InP substrate. The HEMTs enable low-noise amplifiers and RF switches for switched transmit/receive channels.



Figure 4. InP/GaN wafer stacking: schematic cross-section of the technology, and a FIB/SEM cross-section of the completed process.

Our standard InP HBT wiring environment utilizes: a benzocyclobutene insulator, which has a dielectric constant of 2.7; three levels of electroplated gold wiring; and thin-film resistor and metal-insulator-metal capacitor passive elements. The InP device is complemented by one made from silicon, using the 130 nm silicon CMOS process at GlobalFoundries. This CMOS technology offers six levels of copper metal wiring and passive circuit elements.

To design the InP and CMOS device layout and simulate the resulting circuit, we use an integrated Cadence process design kit. Its merits, which can be applied to both technologies, include design-rule checking and layout-versus-schematic checking.

To apply Direct Bond Interconnect technology to InP, we modified the standard back-end-of-line wiring environment. Adjustments included improving dielectric adhesion to the substrate and gold wiring, and developing chemical mechanical polishing process for the 100 mm InP substrate. We found that applying successive rounds of plasma-enhanced CVD of silicon dioxide, followed by chemical mechanical polishing, helped to remove non-planarities on the top of the processed wafer. After this, we pattern and etch the polished silicon oxide, and fill with electroplated copper to form the interconnects.

With silicon CMOS wafers, we use a similar process. In this case, once the wafers are bonded, the silicon wafer is ground and polished until it is just 10 μm thick, before bond pads are formed on the backside of the wafer, connecting to CMOS M1.

We have scrutinised the resulting structure with a scanning electron microscope (see Figure 2). Cross-sectional images reveal the InP HBT and CMOS FET, and show that the M1-to-M1 vertical distance between the technologies is approximately 18 μm. This is short enough to ensure a low parasitic interconnect between the metallization layers.

Our structure has been used to make receiver and transmitter beamformer channels operating in the Q-band at 40 GHz. The receiver channel includes an InP HBT low-noise amplifier, an InP HBT/silicon CMOS 3-bit variable gain amplifier, and a InP HBT/silicon CMOS 4-bit phase shifter. Within the transmitter channel there is an InP HBT/silicon CMOS 4-bit phase-shifter, an InP HBT/silicon CMOS 3-bit variable gain amplifier, and an InP HBT power amplifier.

Characterisation of DC and RF performance reveals that the receiver consumes 240 mW, while the transmitter draws 1 W. For the receiver, variable gain control at 40 GHz is 25.1 dB to 30.3 dB, while for the transmitter it is 28.4 dB to 34.6 dB (see Figure 3). In this configuration, the highest gain state's 1-dB bandwidth at around 40 GHz is 10 GHz for the receiver and 8 GHz for the transmitter. The root-mean-square phase error for the receiver and transmitter at 40 GHz are 4.6 and 4.8 degrees, respectively. For the transceiver channel, the saturated RF output power is 20.3 dBm (107 mW) at 40 GHz. According to measurements with a Keysight PNA-X equipped with factory-installed noise figure hardware (impedance tuner and low-noise receiver front-end), the channel noise figure at 40 GHz is approximately 4.2 dB. This is in close agreement with simulations of the standalone low-noise circuit, including bond pad loss, that show a noise figure of 4.0 dB.

Uniting GaN and InP

Thanks to its high bandgap of 3.4 eV, the GaN HEMT combines excellent high-frequency performance with high breakdown voltages. However, these amplifiers can have low-to-moderate gain at millimetre-wave frequencies, so high-power input signals are required to drive them into compression.

One potential solution is to insert a high-efficiency InP driver amplifier before the GaN stage. The large bandwidths available in InP HBT technology permit high power-added efficiency designs at millimetre-wave frequencies.

To ensure optimal heat dissipation for both devices, InP and GaN technologies must be stacked with a back-to-front wafer bond. Another pre-requisite is the use of through-substrate-vias, to electrically interconnect the substrates.

We create the vias by dry etching the InP substrate with a Cl₂-based gas. Using optimized conditions, aspect ratios as high as 8:1 are possible. During the construction of our hybrid structures, we target a 10 μm-deep through-substrate via. After etching, CVD fills the via with tungsten. Any excess is removed with chemical-mechanical polishing, to leave a tungsten via recessed from the InP surface.

Following the formation of the through-substrate vias, we adopt a standard InP device process flow. After back-end-of-line low-κ dielectric and metallization steps, we prepare the topmost wafer surface for planar SiO₂ bonding to a temporary silicon handle wafer. The strength and planarity of this bond allow the InP substrate to be thinned to just 10 μm, revealing the tungsten through-substrate vias.

The next step is the addition of a copper Direct Bond Interconnect pattern on the thinned backside of the InP substrate. This is united to the GaN-on-SiC substrate with an electrically active bond, before the silicon handle is removed with a combination of grinding and dry etching.



Figure 5. Thermal vias allow thinned InP to provide the equivalent degree of thermal management as a baseline device, according to measurements of the temperature of the base-emitter junction.

Inspecting a cross-section of this structure, using scanning electron microscopy, reveals that the final InP thickness is less than the 10 μm target "“ it is just 4 μm (see Figure 4). This shortcoming will be addressed with a modified through-substrate via reveal process that will ensure a consistent wafer thinning for future lots.

Our InP HBTs and GaN HEMTs have been characterized for DC and RF performance. Measurements on pre- and post-bonding structures reveal that characteristics remain similar before and after integration.

Despite thinning InP to well below its target value, devices retain their performance, even though they sit on top of high thermal resistance materials, such as SiO₂ and benzocyclobutene. Success stems from the thermal vias, which shunt heat from the InP substrate into the low thermal resistance SiC substrate.

Our work highlights the benefits of 3D wafer stacking in compound semiconductor circuit designs. Thanks to our RF beamformer R&D efforts, using various heterogeneous integration strategies, 3D stacking has been shown to provide compact circuit designs for RF and mixed signal millimetre-wave applications.