Laying Foundations For Vertical Transistor Manufacture
Semiconductor Physics made great strides in the twentieth century. Studies of this form of material in the early 1900s led to an understanding of its basic properties, along with techniques on how to dope it. Further progress came in 1947, when a team at Bell Labs produced the first point contact transistor, and three key milestones followed in the 1950s: the first single crystal germanium in 1952; the first single crystal silicon in 1954; and then, in 1958, the first IC, thanks to efforts at Texas Instruments.
Rapid improvements in the IC followed, spawning the creation of the silicon industry. And in 1965, Gordon Moore quantified the rapid rate of progress: according to his prediction, now known as ‘Moore’s Law’, the transistor density on a chip would double every 18 months. This is accomplished by scaling the dimensions of the transistor, a move that must go hand-in-hand with improvements in the performance of the device. To help engineers adhere to this, in 1974 Robert Dennard and co-workers at IBM proposed a set of rules for transistor scaling.
Keeping pace with Moore’s Law, while following the guidelines of Dennard, has led to a period of extensive scaling. Performance and power specifications have been fulfilled at every new node, allowing the cost per chip to plummet. The enabler behind all this progress has been the innovation in process integration (see Figure 1).
Up until about a decade ago, advances in lithography held the key to performance improvement. But in recent times, there have been issues that can’t be addressed by just lithography, so other innovations have had to drive progress.
One of the big changes to the transistor has been the replacement of the SiO2 dielectric with HfO2. Driving this change is that the shrinking of the MOSFET leads to an increase in gate leakage current, due to direct tunnelling, so to combat this, Intel introduced HfO2/metal gates in its 45 nm technologies that were introduced in 2007.
Another recent challenge has been maintaining a reduction in power density. For many years, decreasing the applied voltage did the trick. However, that is no longer an option for silicon, with reductions in voltage compromising on-state performance. To address this, chipmakers introduced multi-core architectures in 2006, at the 65 nm node, and source/drain stressors in the year that followed at the 45 nm node.
Today, production has reached the 10 nm node. Further scaling will increase the severity of shortchannel effects, leading to a higher leakage current. This issue has led to concerns for device reliability at future nodes, and it threatens to halt improvement in device performance. To maintain the pace of progress, there needs to be innovation related to the gate stack, channel materials, device architectures and circuit designs.
Figure 1. Innovation in process integration is the real enabler of Moore’s law
Mitigation of short-channel effects can be realized with a gate-all-around nanowire FET architecture, which provides superior electrostatic control (see Figure 2). A full circuit architecture is yet to be developed, but vertical channel designs are offering a compact footprint, constrained by the contacted-gate pitch. There is the possibility to relax physical gate length and even channel thickness with respect to lateral nanowires or FinFETs.
Figure 2. Different device architectures: triple-gate finFET, lateral gate-all around nanowire FET (GAA-NWFET) with one or more wires stacked horizontally on top of one another, and vertical GAA-NWFET with multiple wires stacked vertically next to each other. Figure taken from A. Veloso et al. ECS Trans. 2016
This new architecture is not just a solution for silicon. In fact, it offers even more promise for III-V channels, as they are severely challenged by channel thickness scalability, due to much stronger size-quantization effects. This issue stems from the lighter isotropic bulk electron effective mass for III-Vs than for silicon.
One of the most promising emerging devices is the tunnel FET, which could lead to far lower operating voltages. For this form of transistor, it makes sense to employ vertical channels, due to the need for complex epitaxial heterojunctions and the asymmetric source-drain overlap. Given this state of affairs, there is a need to investigate methods for realising highquality III-V vertical nanowire devices. At imec, we are pursuing this, with efforts directed at addressing the rising demand for innovations in process integration.
Any attempts at developing these alternate channel devices must use the silicon substrate as the foundation. Taking this approach ensures that the technology can take advantage of the mature silicon CMOS process, and enable co-integration of different functionalities. The challenge is that the growth of III-Vs on silicon is not easy: these are two markedly different material systems, with mismatches in lattice constants, thermal expansion coefficients and polarities.
Our focus is the investigation of InGaAs vertical nanowire devices, produced with an ‘industry-friendly’ approach. The idea is to grow stacks of InGaAs inside trenches, defined in a 300 mm diameter silicon wafer, before a top-down technique is applied, creating nanowires with diameters down to 30 nm using patterning and dry-etching steps. However, to speed our development, we have begun by using InGaAs grown on a lattice-matched InP substrate, to ensure good quality layers.