IRPS: How robust is the SiC MOSFET?

Researchers at the International Reliability Physics Symposium report the results of investigations into the impact of defects and gate oxide quality on the performance of the SiC MOSFET

BY RICHARD STEVENSON

ΩThe SiC MOSFET is guaranteed of great future. Thanks to its capability to efficiently control current at high voltages, sales are accelerating in a multitude of applications, including electric vehicles, solid-state circuit breakers, and various types of motors. Multi-billion dollar revenues are sure to follow.

However, exactly how much success the SiC MOSFET will have is not set in stone. Factors weighing heavily on this are price, performance, and reliability. And of these three, reliability is arguably the most critical. That’s because many the adopters of this device will really value robustness, as this allows them to foster a reputation for producing products that never fail.

Efforts within the SiC community continue to take the reliability of the SiC MOSFET to a new level. At the recent International Reliability Physics Symposium (IRPS), a forum with a rich history in considering the long-term health of silicon devices, several presentations considered the robustness of the SiC MOSFET. At this meeting, held on-line due to Covid-19 restrictions, the likes of Infineon, STMicroelectronics and On Semiconductor provided insights into the impact of defects on the lifetime of the device, and offered options for assessing reliability of the gate oxide.

Hidden assassins
Today, most SiC devices are produced using 150 mm SiC substrates. The quality of this foundation has improved a great deal over the last two decades. However, even state-of-the-art substrates grown by physical vapour transport are far from perfect. It is the norm for them to have around ten thousand defects per square centimetre, according to conference speaker Thomas Neyer from On Semiconductor.

Neyer’s presentation considered many different forms of defect that occur in SiC MOSFETs. He explained that one common option for exposing them is to treat the material in molten potassium hydroxide, and then examine the wafer with a microscope. But he prefers to classify defects with non-destructive approaches, such as photoluminescence techniques, X-ray topography and imaging with cross-polarised light. Using these techniques to record defects allows the performance of devices to be correlated with the type of imperfection. So powerful is this approach that it is even possible to relate device performance to the actual number of defects in a particular die.

It would be easy to blame all the defects found in epiwafers on imperfections in the boule. That’s misleading, however, explained Neyer, who pointed out that they can also be introduced in the slow and costly wafering process flow, involving slicing, grinding and polishing. When substrates are formed from a boule, this creates nanoscale dislocations with open cores that hamper the quality of SiC epilayers.

Neyer and his co-workers have categorised the defects found in SiC epilayers into three groups: killer visible defects, which include triangular types of defect, strong topographic defects and carrots; non-killer visible defects, such as obtuse triangles, scratches, pits and V-type defects; and non-killer crystal defects, such as stacking faults, basal plane dislocations, grain boundaries and bar stacking faults (see Figure 1 for more details).

Figure 1. Researchers at On Semiconductor have categorised SiC defects into three classes: killer visible defects (left), non-killer visible defects (middle), and non-killer crystal defects (right). Examples of killer visible defects are (a) triangular defects, (b) particle triangles, (c) particles/downfalls, (d) strong topographic defects and (e) carrots. Non-killer visible defects include (f) obtuse triangles, (g) scratches, (h) pits, (i) V-type defects, (j) roughness/step bunching and (k) small topographic defects. Non-killer crystal defects include (l) stacking faults, (m) basal plane dislocations, (n) bar stacking faults, and (o) grain boundaries.

Investigations at On Semiconductor have uncovered the impact of non-killer defects through a study that has considered around 3 million devices with a 9 mm² die size – they are a combination of Schottky diodes and MOSFETs. According to Neyer, this survey showed that a significant proportion of devices have five or more defects per die. This begs the question: does device performance drop off with more non-killer defects?

The answer is nuanced. For Schottky barrier diodes, an increase in non-killer defects has little impact; but for MOSFETs, the opposite is true – and when a die has more than 10 non-killer defects, this is more of concern than a killer defect. Non-killer defects are to blame for early life rejects, burn-in failures, and outliers in short circuits and avalanche tests.

Neyer and co-workers also discovered that SiC MOSETs with double-digit numbers of stacking faults have a wider distribution in key device characteristics. Average values for the leakage current and its standard deviation both increase markedly, while values for the breakdown voltage and threshold voltage – these depend on extraction currents – decrease as the number of stacking faults per die increases.

Another investigation by the team from On Semiconductor considered bipolar degradation in the SiC body diode of the MOSFET. This technique, widely employed for evaluating 3.3 kV devices, has been applied by Neyer and co-workers to MOSFETs designed to handle 1200 V and 1700 V. After stressing these devices for between one and three days with a DC drain-source current of 60 A cm^-2 and a gate-source voltage of -5 V, the engineers found that the greater the basal plane dislocations per die, the greater the shift in on-current. For 1200 V devices, the team recorded an increase in on-current of almost 2 percent for a die with 35 basal plane dislocations, while for the 1700 V equivalent, 30 basal plane dislocations were behind an up-tick in on-current of almost 7 percent.

Encouraging results have come from benchmarking the threshold voltage stability of On Semiconductor’s MOSFETs against rival SiC products with planar and trench architectures. Using a gate-source stress at 100 kHz and a 50 percent duty cycle, this device exhibited greater stability than its three competitors used in this study (see Figure 2).

Figure 2. Engineers at On Semiconductor benchmarked their SiC MOSFET against that of three competitors using a gate-source stress at 100 kHz and a 50 percent duty cycle.

Troublesome triangles
Studies of the role of defects on the MOSFET’s breakdown have also been conducted by a team from CNR-IMM, Italy, working in collaboration with STMicrolectronics. Speaking on behalf of this partnership, Patrick Fiorenza from CNR-IMM argued that efforts to understand infant mortality have to begin with wafer level tests involving thousands of devices. He pointed out that it is critical to differentiate between extrinsic breakdown, which happens during the early life of a device, and intrinsic breakdown.

Fiorenza provided an example of a device that had failed instantly. Imaging this device by emission microscopy and scanning electron microscopy revealed a surface pit, which has a hexagonal nature, according to differential atomic force microscopy. When the team delved more deeply into this imperfection with cross-sectional scanning electron microscopy, they found a region with a polytype within the substrate. Weighing up the implications of this finding, Fiorenza concluded: “We have to take care of the fabrication steps, in particular the epitaxial growth of the material.”

He added explained that when working at the buffer level, it is also worthwhile to check the gate current: “This is important to understand if some extrinsic failure can be intercepted before finalisation of the fabrication.” At very low electric fields – such as just 4 MV/cm, which ensures no threat of insulator damage – he and his co-workers have found that it is possible to observe gate currents that don't follow the ideal Fowler-Nordheim behaviour. Looking at devices with this attribute in more detail, the team have identified compromised devices that failed high-temperature gate bias tests, due to surface bumps that are seen in atomic force microscopy images.

Devices passing this test were packaged, before undergoing a high-temperature stress test at a 600 V reverse bias. The 2 percent of devices that failed this test, lasting 3 months and involving an elevated temperature of 140 ºC, exhibited a hike in gate current of around seven orders of magnitude. In addition, their characteristics changed dramatically, such as moving to normally-on behaviour.

Imaging the surface of the device with a focused ion beam failed to shed any light on the cause of failure of the MOSFETs. So Fiorenza and co-workers removed the poly-silicon metal gate and the gate oxide, before inspecting the structure once more. This time they discovered triangular defects in the JFET region of the MOSFET. Using a two-beam form of transmission electron microscopy, they found a mixed edge and screw dislocation.

Additional analysis of this stripped back sample, using other forms of probe-based microscopy, enhanced the team’s understanding of this imperfection and its consequences. Local current measurements revealed an increase in two order of magnitude in the conductivity around the threading dislocation, and scanning capacitance microscopy measurements, considering the phase of the signal, revealed local variations in minority carrier concentration and identified a charge distribution associated with the triangular defect (see Figure 3). After drawing on reports in the scientific press, Fiorenza accounted for this observation by reasoning that the threading dislocation has an increased hole concentration and a bandgap that is 0.8-1 eV lower than the surrounding SiC. Simulations supported this view the team and enabled the team to discover that threading dislocations act as quantum wells, increasing hole concentration by 13 orders of magnitude. Operating in reverse bias, these holes are driven through the SiO₂ layer of the MOSFET, accelerating its degradation.

Figure 3. Investigations of threading dislocations by a partnership between CNR-IMM and ST Microelectronics have involved scanning capacitance microscopy measurements. A map of the amplitude of this signal (right) reveals a constant doping concentration; the phase of the signal (left) uncovers local variations in minority carrier concentration, and enables identification of a charge distribution associated with a triangular defect.

Speeding screening
Those needing to assess the reliability of the SiC MOSFET will welcome the introduction of a relatively straightforward, speedy technique developed by Infineon Technologies and announced at IPRS. This approach focuses on the weakness of the gate oxide, which is the key failure mechanism.

Speaking on behalf of Infineon, Judith Berens detailed this powerful technique after laying the groundwork – the distinction between the intrinsic and extrinsic branch of gate oxide reliability. “The intrinsic branch only plays a role towards the end of the life, and is similar for SiC and silicon MOSFETs,” explained Berens. “Extrinisics, however, might lead to early failures in the field, and for this reason need to be avoided.”

Failures due to extrinsics are a significant cause for concern, given that their prevalence is higher in SiC MOSFETs than in silicon devices. One promising option for uncovering them is to measure device performance at different voltages. “By gate-voltage screening, you mainly sort out devices with extrinsics, and reduce the field failure probability,” said Berens.

The extent of failure reduction realised by screening depends on the ratio of the screening voltage to the operating voltage – Berens refers to this as the failure reduction factor. Note that this factor exceeds a thousand when the screening voltage is three times the value of the recommended operating voltage (see Figure 4).

Figure 4. Engineers at Infineon have drawn on previous work (Aichinger and Schmidt, IRPS2020, 3B4_042) that relates a failure rate reduction factor to the ratio of the screening voltage (V_GS,scr) to the recommended gate use voltage provided by a datasheet (V_use). Combining this relationship with rapid stress tests enabled a comparison of the reliability of SiC MOSFETs produced by various vendors.

Of course, there are limitations on how high a voltage can be used for screening. This method of evaluation must avoid an permanent damage to ‘good’ chips, accomplished by avoiding degradation caused by the tunnelling of carriers and impact ionisation. Both phenomena can lead to a negative threshold voltage shift.

Berens championed a new measurement procedure that avoids using too high a stress voltage. Instead, a series of voltages are applied, each 1 V higher than the previous. After each pulse, which should be as short as possible to reduce the chances of degradation, the threshold voltage is recorded.

To illustrate the value of this approach, Berens presented an example of what one could expect when carrying out this measurement. To begin with, as the stress voltage incrementally increased, so did the threshold voltage, due to a positive bias temperature instability. But beyond a certain value the threshold voltage plummeted, reaching a point of no return and causing the device to be irreversibly damaged (see Figure 5).

Figure 5. Infineon has developed a new form of stress test for SiC MOSFETs. A series of voltages are applied, each 1 V higher than the previous one, and the threshold voltage is recorded. As the stress voltage incrementally increases, initially the threshold voltage increases as well, due to a positive bias temperature instability. But beyond a certain value the threshold voltage plummets and the device is irreversibly damaged.

Berens explained that determining the likelihood of field-rate failure requires the value for the stress voltage for the onset of irreversible degradation, along with the intended operating voltage for the MOSFET. The ratio of these two determines the failure reduction factor and gives an insight into device reliability.

Demonstrating how this works in practice, Berens compared data for a range of commercial MOSFETs, including trench and DMOS designs. Pulsed stress tests uncovered a 20 V range in voltages required to reach the onset of irreversible damage, with values depending on the thickness of the oxide. This is understandable, as thicker oxides are subjected to a weaker electric field strength that reduces the chances of impact ionisation.

For the next step in this analysis, Berens and co-workers accounted for the operating voltage of the various devices. With this factor included, the differences between manufacturers narrowed significantly; and the new, normalised ratio allowed the failure rate reduction factor to be determined by reading this value from the graph shown in Figure 4. Note that due to the high degree of non-linearity of this graph, small variations in the normalised ratio produce a difference in the failure rate reduction factor by two orders of magnitude (see Figure 6). This implies that the most reliable devices have roughly one hundred times fewer failures in the field than the most unreliable devices.

Figure 6. Research at Infineon has uncovered a difference in the failure rate reduction factor of two orders of magnitude between SiC MOSFETs made by different manufacturers. This implies that the most reliable devices have roughly one hundred times fewer failures in the field than the most unreliable devices.

Berens says that one of the advantages of this method is the speed with which it determines the likelihood of failure – it takes less than a minute per test run. The technique is also straightforward, with no special test equipment required. “And last but not least, we didn’t need any special knowledge, only publicly available data sheet values.”

The problem of pits
SemiQ, a producer of SiC power devices based in California, has also been investigating the screening of SiC MOSFETs using the gate voltage. Speaking on behalf of the company, Yongju Zheng detailed measurements on 1200 V, 80 Ωm SiC planar DMOSFETs with a 50 nm-thick gate oxide. This investigation considered a variety of voltages and voltage ramp rates, with measurements taken at room temperature and 130ºC.

Zheng and co-workers have pursued a two-step process. In their study, they began by ramping from 40 V to 50 V, which screened out about 4 percent of devices from the sample size of 289. “These are defined as weak gate oxides, as the median voltage of our devices is about 53-54 volts,” said Zheng. The second step involved ramping from 40 V and 70 V. The upper end ensured breakdown and enabled a failure distribution to be obtained. Failure is defined when gate leakage hits 9 mA.

The engineers found that the failure voltage is higher when the ramp rate is faster. “This could be due to longer stress time, leading to more charging at the interface of silicon carbide and silicon dioxide,” speculated Zheng. Note that for the two temperatures used in study, no notable difference in failure voltage is found.

Zheng and her colleagues have considered whether large epi pits could be behind the early failure of some SiC MOSFETs. “It turned out that these early failures show very strong correlation to large pit defects, that are defined as pit defects larger than 100 micron-squared.” This correlation is so strong that 80 percent of these large pits caused early failure (see Figure 7). According to Zheng, the presence of these pits may alter the epitaxial growth conditions, and lead to local oxide thinning that would result in electric field crowding – both factors could account for early failures.

Figure 7. A study at SemiQ has shown that when pit defects are larger than 100 µm2, 80 percent of them cause early failure of a SiC MOSFET.

One of the downsides of using a high screening voltage is that it causes a negative shift in the threshold voltage, which could impair reliability, especially when operating the MOSFET at high temperatures under reverse bias. Measurements by the team from SemiQ have shown that ramping from 40 V to 50 V produces a negative shift in the threshold voltage of 0.85 V, taking this device close to normally-on behaviour.

“Based on the study in this work, the screening voltage is suggested to be below 38 volts for a 50 nanometre gate oxide in production,” said Zheng, adding that such a value should be low enough to detect the extrinisic failure rate, while not significantly lowering the threshold voltage of the MOSFET, or shortening the lifetime of its gate oxide.

Looking into leakage
A thorough study into the leakage current of 1.2 kV commercial SiC power MOSFETs has been conducted by researchers at Ohio State University, working in partnership with engineers at Alpha and Omega Semiconductor.

Highlighting the findings at IPRS, Shengnan Zhu from Ohio State University explained that one of the challenges with this type of study is that the device makers do not disclose the thickness of their gate oxides. So Zhu and her co-workers have had to estimate this from the value for the breakdown voltage, obtained by measuring the gate leakage current while ramping the gate voltage. This approach indicated that the oxide in 1.2 kV power MOSFETs varies from 39 nm to 46 nm, assuming a dielectric breakdown field in the range 10 MV/cm to 11.5 MV/cm.

The team also recorded variations in the gate current leakage over a 24 hour period for a range of gate voltages, while maintaining the device at an elevated temperature of 150ºC. Plotting the data revealed three regimes (see Figure 8). For gate voltages of 39 V or more, the gate current accelerates; for voltages of 38 V to 35 V, there are variations in the current, before a rapid hike; and for a voltages of 33 V or less, the current falls steadily.

Figure 8. Researchers have identified three different regimes for SiC MOSFETs subjected to gate-stress tests. When the gate voltage is 39 V or more, the gate current accelerates; for voltages of 38 V to 35 V, initially the current varies, before a rapid hike; and for a voltages of 33 V, current falls steadily.

Zhu offered a detailed explanation for this range of behaviour. She argued that for gate voltages of 39 V or more, corresponding to an oxide field of 9.8 MV/cm or more, hole trapping dominates. This takes place due to Fowler-Nordheim tunnelling of electrons into the device – these carriers trigger impact ionisation and generate electron-hole pairs, with holes driven to the semiconductor-oxide interface, where they are joined by additional holes resulting from anode hole injection. A high hole density at this boundary reduces in the width of the barrier for tunnelling of electrons and leads to an increased injection of this carrier, which generates yet more holes through impact ionisation. With positive feedback at play, there is an acceleration of the gate leakage current.

For voltages of 38 V to 35 V, the oxide field is slightly lower, at 9.5-9.0 MV/cm. In this case, there is also hole trapping that enhances the electric field near the interface. However, this time subsequent electron trapping in the oxide leads to a reduction in the strength of the local field, a widening of the tunnel barrier, and ultimately a reduction in leakage current. Dominance of hole trapping, followed by electron trapping, results in a rise and then a fall in the gate leakage current. When investigating this in more detail, the team found that their conjecture is supported by variations in threshold voltage.

When the gate voltage is 35 V or below, the field across the gate oxide is restricted to no more than 8.8 MV/cm. For devices operating in this regime, electron trapping takes place, relaxing the electric field. This increases the barrier width, and in turn reduces Fowler-Nordheim tunnelling. While this takes place, the threshold voltage increases.

The insights provide by Zhu and the other speakers at IPRS showcase the progress being made to understand the reliability of the SiC power MOSFET, and differences in the devices of many manufacturers. As insights feed in to device development and production, robustness of this transistor should increase, driving its deployment in ever more applications.