Conference Report

This article was originally featured in the edition: Volume 27 Issue 4

IRPS: How Robust Is The SiC MOSFET?

News

Researchers at the International Reliability Physics Symposium report the results of investigations into the impact of defects and gate oxide quality on the performance of the SiC MOSFET BY RICHARD STEVENSON

ΩThe SiC MOSFET is guaranteed of great future. Thanks to its capability to efficiently control current at high voltages, sales are accelerating in a multitude of applications, including electric vehicles, solid-state circuit breakers, and various types of motors. Multi-billion dollar revenues are sure to follow.

However, exactly how much success the SiC MOSFET will have is not set in stone. Factors weighing heavily on this are price, performance, and reliability. And of these three, reliability is arguably the most critical. That's because many the adopters of this device will really value robustness, as this allows them to foster a reputation for producing products that never fail.

Efforts within the SiC community continue to take the reliability of the SiC MOSFET to a new level. At the recent International Reliability Physics Symposium (IRPS), a forum with a rich history in considering the long-term health of silicon devices, several presentations considered the robustness of the SiC MOSFET. At this meeting, held on-line due to Covid-19 restrictions, the likes of Infineon, STMicroelectronics and On Semiconductor provided insights into the impact of defects on the lifetime of the device, and offered options for assessing reliability of the gate oxide.

Hidden assassins
Today, most SiC devices are produced using 150 mm SiC substrates. The quality of this foundation has improved a great deal over the last two decades. However, even state-of-the-art substrates grown by physical vapour transport are far from perfect. It is the norm for them to have around ten thousand defects per square centimetre, according to conference speaker Thomas Neyer from On Semiconductor.

Neyer's presentation considered many different forms of defect that occur in SiC MOSFETs. He explained that one common option for exposing them is to treat the material in molten potassium hydroxide, and then examine the wafer with a microscope. But he prefers to classify defects with non-destructive approaches, such as photoluminescence techniques, X-ray topography and imaging with cross-polarised light. Using these techniques to record defects allows the performance of devices to be correlated with the type of imperfection. So powerful is this approach that it is even possible to relate device performance to the actual number of defects in a particular die.

It would be easy to blame all the defects found in epiwafers on imperfections in the boule. That's misleading, however, explained Neyer, who pointed out that they can also be introduced in the slow and costly wafering process flow, involving slicing, grinding and polishing. When substrates are formed from a boule, this creates nanoscale dislocations with open cores that hamper the quality of SiC epilayers.

Neyer and his co-workers have categorised the defects found in SiC epilayers into three groups: killer visible defects, which include triangular types of defect, strong topographic defects and carrots; non-killer visible defects, such as obtuse triangles, scratches, pits and V-type defects; and non-killer crystal defects, such as stacking faults, basal plane dislocations, grain boundaries and bar stacking faults (see Figure 1 for more details).


Figure 1. Researchers at On Semiconductor have categorised SiC defects
into three classes: killer visible defects (left), non-killer visible
defects (middle), and non-killer crystal defects (right). Examples of
killer visible defects are (a) triangular defects, (b) particle
triangles, (c) particles/downfalls, (d) strong topographic defects and
(e) carrots. Non-killer visible defects include (f) obtuse triangles,
(g) scratches, (h) pits, (i) V-type defects, (j) roughness/step bunching
and (k) small topographic defects. Non-killer crystal defects include
(l) stacking faults, (m) basal plane dislocations, (n) bar stacking
faults, and (o) grain boundaries.



Investigations at On Semiconductor have uncovered the impact of non-killer defects through a study that has considered around 3 million devices with a 9 mm2 die size - they are a combination of Schottky diodes and MOSFETs. According to Neyer, this survey showed that a significant proportion of devices have five or more defects per die. This begs the question: does device performance drop off with more non-killer defects?

The answer is nuanced. For Schottky barrier diodes, an increase in non-killer defects has little impact; but for MOSFETs, the opposite is true - and when a die has more than 10 non-killer defects, this is more of concern than a killer defect. Non-killer defects are to blame for early life rejects, burn-in failures, and outliers in short circuits and avalanche tests.

Neyer and co-workers also discovered that SiC MOSETs with double-digit numbers of stacking faults have a wider distribution in key device characteristics. Average values for the leakage current and its standard deviation both increase markedly, while values for the breakdown voltage and threshold voltage - these depend on extraction currents - decrease as the number of stacking faults per die increases.

Another investigation by the team from On Semiconductor considered bipolar degradation in the SiC body diode of the MOSFET. This technique, widely employed for evaluating 3.3 kV devices, has been applied by Neyer and co-workers to MOSFETs designed to handle 1200 V and 1700 V. After stressing these devices for between one and three days with a DC drain-source current of 60 A cm-2 and a gate-source voltage of -5 V, the engineers found that the greater the basal plane dislocations per die, the greater the shift in on-current. For 1200 V devices, the team recorded an increase in on-current of almost 2 percent for a die with 35 basal plane dislocations, while for the 1700 V equivalent, 30 basal plane dislocations were behind an up-tick in on-current of almost 7 percent.

Encouraging results have come from benchmarking the threshold voltage stability of On Semiconductor's MOSFETs against rival SiC products with planar and trench architectures. Using a gate-source stress at 100 kHz and a 50 percent duty cycle, this device exhibited greater stability than its three competitors used in this study (see Figure 2).


Figure 2. Engineers at On Semiconductor benchmarked their SiC MOSFET
against that of three competitors using a gate-source stress at 100 kHz
and a 50 percent duty cycle.


Troublesome triangles
Studies of the role of defects on the MOSFET's breakdown have also been conducted by a team from CNR-IMM, Italy, working in collaboration with STMicrolectronics. Speaking on behalf of this partnership, Patrick Fiorenza from CNR-IMM argued that efforts to understand infant mortality have to begin with wafer level tests involving thousands of devices. He pointed out that it is critical to differentiate between extrinsic breakdown, which happens during the early life of a device, and intrinsic breakdown.

Fiorenza provided an example of a device that had failed instantly. Imaging this device by emission microscopy and scanning electron microscopy revealed a surface pit, which has a hexagonal nature, according to differential atomic force microscopy. When the team delved more deeply into this imperfection with cross-sectional scanning electron microscopy, they found a region with a polytype within the substrate. Weighing up the implications of this finding, Fiorenza concluded: “We have to take care of the fabrication steps, in particular the epitaxial growth of the material.”

He added explained that when working at the buffer level, it is also worthwhile to check the gate current: “This is important to understand if some extrinsic failure can be intercepted before finalisation of the fabrication.” At very low electric fields - such as just 4 MV/cm, which ensures no threat of insulator damage - he and his co-workers have found that it is possible to observe gate currents that don't follow the ideal Fowler-Nordheim behaviour. Looking at devices with this attribute in more detail, the team have identified compromised devices that failed high-temperature gate bias tests, due to surface bumps that are seen in atomic force microscopy images.

Devices passing this test were packaged, before undergoing a high-temperature stress test at a 600 V reverse bias. The 2 percent of devices that failed this test, lasting 3 months and involving an elevated temperature of 140 ºC, exhibited a hike in gate current of around seven orders of magnitude. In addition, their characteristics changed dramatically, such as moving to normally-on behaviour.

Imaging the surface of the device with a focused ion beam failed to shed any light on the cause of failure of the MOSFETs. So Fiorenza and co-workers removed the poly-silicon metal gate and the gate oxide, before inspecting the structure once more. This time they discovered triangular defects in the JFET region of the MOSFET. Using a two-beam form of transmission electron microscopy, they found a mixed edge and screw dislocation.

Additional analysis of this stripped back sample, using other forms of probe-based microscopy, enhanced the team's understanding of this imperfection and its consequences. Local current measurements revealed an increase in two order of magnitude in the conductivity around the threading dislocation, and scanning capacitance microscopy measurements, considering the phase of the signal, revealed local variations in minority carrier concentration and identified a charge distribution associated with the triangular defect (see Figure 3). After drawing on reports in the scientific press, Fiorenza accounted for this observation by reasoning that the threading dislocation has an increased hole concentration and a bandgap that is 0.8-1 eV lower than the surrounding SiC. Simulations supported this view the team and enabled the team to discover that threading dislocations act as quantum wells, increasing hole concentration by 13 orders of magnitude. Operating in reverse bias, these holes are driven through the SiO2 layer of the MOSFET, accelerating its degradation.