2D transistors look to extend the logic roadmap

Development of WS2 2D transistors in a 300 mm CMOS fab provides a promising pathway for scaling the transistor

BY INGE ASSELBERGHS AND IULIANA RADU FROM IMEC

The era of ‘happy scaling’, driven by Moore’s Law and played out by the semiconductor community, has faced severe challenges since 2005. Up until then progress came relatively easily, with shrinking of the silicon transistors delivering multiple benefits, including a lower power consumption, increased performance, and a reduction in the fabrication cost per transistor. A new, more powerful generation of technology launched roughly every two years – denoted by a new node size – to double the number of transistors packed into an identical-sized chip.

The first sign that the benefits of scaling would not go on forever appeared when the node-to-node performance improvements at a fixed power – referred to as Dennard scaling – started slowing down. Applying the brakes were short-channel effects. Leakage currents started shooting up, even when not applying a voltage to the gate, due to significant reductions in gate length and a shortening of the conduction channel. Scaling also caused source and drain contacts to begin to have a dramatic impact on the channel region.

To compensate for this slow-down in device improvement and allow integrated circuits to continue to advance, much effort has been directed at developing new transistor technologies. Many directions have been pursued, including new channel materials, new transistor architectures and co-optimisation of the chip’s design and its technology.

A significant architectural improvement has been the replacement of the planar MOSFET with the FinFET – the latter is now the incumbent design in mainstream chip production processes. In a FinFET, the channel takes the form of a very thin fin, positioned between source and drain terminals. Wrapping around this three-dimensional channel is a gate that provides control from three sides and combats short-channel effects. It is an architecture that has been crucial to scaling over the last decade, but will fail to provide enough electrostatic control beyond the 5 nm or 3nm node.

Building on this approach is the vertically stacked, gate-all-around nanosheet transistor. It provides superior channel control, thanks to a gate that fully wraps around and in between the channels. At imec of Leuven, Belgium, this architecture is on our roadmap, followed by the forksheet transistor – that is a design that uses a forked gate structure to control nanosheets, and allows a far tighter n-to-p spacing than that possible with FinFET and nanosheet devices. Another candidate for well into the future is a stack of multiple channels, which could effectively extend scaling with silicon or SiGe semiconductors.

Running in parallel to this evolution, the researcher community has been investigating gains provided by enhancing carrier mobility. Options for the channel include strain engineering and migrating to high-mobility semiconductors, such as germanium and the III/-Vs. Note that there is much interest in InGaAs: as it transports charge much faster than silicon, it promises faster speeds and lower power consumption. Innovative processes have already been developed to incorporate foreign channels with silicon CMOS, using conventional manufacturing techniques. However, just like silicon, it is unlikely that these high-mobility materials will enable sufficient gate length scaling at the very advanced nodes that lie ahead. It seems that III/V-material-based devices will find a more natural adoption in high-frequency applications – as required for (beyond-) 5G applications – that allow their high-speed properties to reach their full potential.

The promise of 2D semiconductors
To realise further gate length reduction, thinner semiconductor channels are needed to keep short channel effects under control. Migrating to thinner channels restricts the pathway for current to flow, and this limits the opportunity for charge carriers to leak when the device is turned off.

Offering much promise in this regard is a class of material known as two-dimensional semiconductors. They include transition metal dichalcogenides, such as WS₂ and MoS₂. In these semiconductors atoms are arranged in layered crystals, with a single layer thickness of typically just 7Å – small enough to make these materials a great choice for ensuring very thin channels. Results from theoretical studies highlight their potential, indicating that they maintain a relatively high carrier mobility, independent of channel thickness. It’s an attribute that should enable engineers to scale gate lengths below 10 nm without having to worry about short channel effects.

Working within the Design-Technology Co-Optimization framework, our team at imec has recently highlighted the potential for transistors with a 2D semiconductor channel to further extend the logic scaling roadmap. We anticipate that these 2D-FETs, which will most probably find their insertion point in a stacked-nanosheet-like architecture, will extend the roadmap by providing at least two technology generations. Our circuit-level evaluation of power, performance and area at a node with 36nm gate pitch revealed that transition metal dichalcogenides in a stacked 2D-nanosheet configuration outperform silicon-based counterparts while having a reduced footprint. Note that this model employed realistic assumptions, drawing on as much experimental data as possible.

The global effort at developing transition metal dichalcogenides has led to the exploration of a variety of materials, and the identification of some of the main challenges for improving device performance. To date, most work has involved semiconductor channels made of MoS2. Devices based on this material are the most mature, with the best experimental values for mobility getting close to the theoretical value of 200 cm²/Vs.

Recently, promising results have been reported for WS2-based FETs. According to theoretical work, these devices have the potential to deliver an even higher performance than their MoS₂ cousins. Experimental results are also encouraging. For example, back in 2019, research reported by a TSMC-led collaboration showed that electrical characteristics, such as the on/off ratio and the sub-threshold swing, are comparable to the best recently published values for MoS₂ n-FETs. In its turn, imec has demonstrated functional 2D-FETs with a 30 nm-long channel just 1-2 monolayers thick.

Figure 1. Design-Technology Co-Optimization (DTCO) analysis suggests that stacked 2D materials with side contacts are needed to compete with silicon nanosheets.

With this class of devices a dual-gated device structure improves electrostatic control. Unlike traditional FETs, which just have a gate at the top, dual-gated siblings have a top and a bottom gate – when connected, this increases electrostatic control over the channel. Measurements on our 2D-FETs with connected top and back gates reveal that they outperform single-gated counterparts in drive current (Ion), transconductance and sub-threshold swing, three key metrics for evaluating short-channel effects. Another encouraging aspect of the dual-gate structure is that it shows promise for CMOS operation.

While these results suggest that a great future lies ahead for the WS₂-based FET, there is much work still to do, given that the devices we’ve just described were fabricated on relatively small coupons with patches of synthetic transition metal dichalcogenide material. To build on these hero results from lab-based devices and prepare a pathway for commercial success, an approach must be found that enables their adoption in a 300 mm integration flow.

A 300 mm platform
Several years ago, our team started working towards 300 mm integration of the family of transition metal dichalcogenide 2D semiconductors. This created in a unique 300 mm test vehicle for 2D-FETs, allowing fabrication of functioning devices with gate lengths down to 18 nm. We have used the flow to study the impact of various processing conditions, such as channel deposition technology and gate stack formation. Based on these insights, we are developing improved process steps to enhance device performance.

Figure 2. Atomic force microscopy of films of WS2 grown by MOCVD at (left) 750°C and (right) 950°C (as presented at the 2020 IEDM conference).

Our first foray into the formation of integrated transistors on the 300 mm platform pointed to high-temperature MOCVD as the best option for depositing high-quality channels, critical to realising high-performance devices. This growth technology offers thickness control of the 2D semiconductor down to a single monolayer. However, there are small multi-layer spots over the full 300 mm wafer.

We have found that the growth temperature impacts material quality. This conclusion came from the growth and characterisation of a layer of WS2 deposited at 750°C and 950°C, using W(CO)₆ and H₂S sources. Using atomic force microscopy, we compared films grown on 300 mm silicon/SiO₂ substrates, produced using a growth time of 170 minutes, and found that a higher deposition temperature increases the size of the WS₂ grains. The higher temperature also improves crystallinity and reduces the defectivity of the WS₂ layer, according to photoluminescence and Raman measurements. It is possible that larger crystal sizes could be obtained at lower temperatures using different precursors or other deposition techniques – this is a topic of further research.

One of the challenges associated with producing WS₂ is that it is not easy to deposit insulating materials on top of the 2D surface and form a gate dielectric. An intrinsically passivated process is to blame. When traditional ALD processes are adopted, relying on nucleation of surface dangling bonds, growth only occurs at defect sites. Since the MOCVD-grown WS₂ has relatively few defect sites, this hinders direct oxide deposition.

To tackle this issue, we are investigating novel approaches for oxide deposition. They include making use of a nucleation layer of silicon seeds, deposited by a molecular beam. Another problem we shall have to consider is the low adhesion of the WS₂ to most oxides, resulting from self-passivation. This poses challenges for typical patterning schemes using hard masks.

Results on our devices formed on 300 mm wafers reveal that their performance is an order of magnitude lower than it is for reported lab devices. For example, on-current is typically just 10 µA/µm. To understand why these devices are inferior, we have considered the integrated flow. Our characterisation of dual-gated devices with source/drain side contacts suggests that channel material crystallinity is the biggest challenge to improving device performance. Success requires further breakthroughs in material growth and processing. We also have room for improvement in the processes used to form gates, dope material and add contacts.

As 2D semiconductor-based FETs are most likely to be introduced in stacked nanosheet-like architectures, we have used the 300 mm-compatible flow to identify and overcome challenges associated with building these advanced device architectures. The creation of a stacked nanosheet requires formation of a superlattice structure, containing alternating layers of a channel material and either silicon or SiGe. Once this is formed, nanosheets could be released by selectively etching away the silicon or SiGe layers. Looking further ahead, there may come a time when 2D semiconductors are integrated in a complementary FET (CFET)-like architecture, using n-type 2D-FETs on top of p-type 2D-FETs.

Figure 3. Transmission electron microscopy (TEM) image of a 2D device fabricated with 300 mm processes (as presented at the 2020 IEDM conference).

While MOCVD is the preferred technique for depositing high-quality 2D semiconductor channels, the high temperatures that are used threaten to exceed the thermal budget. Options to prevent this from happening include introducing different precursors and switching to alternative deposition technologies. There is also the more radical, complex approach of using a transfer process to move the 2D channel to a pre-patterned 300 mm silicon wafer.

Evaluating variability
Efforts at imec have not been limited to just developing and integrating 2D-based transistors. We have also undertaken the first-ever variability study of a large set of nanoscale lab-based 2D-FET devices, using transistors with a channel width of 115 nm and lengths of 100 nm and below. Their investigation considered various sources of variability – including the thickness of the 2D-channel; the presence of bilayer islands, such as grains; and the 2D growth template – and the respective impact on electrical performance, with a focus on the sub-threshold regime.

Within this study, there have been simulations, along with the construction of devices that have a median sub-threshold slope of 80mV/dec and maximum on-current in excess of 100 µA/µm. This research uncovered a strongly reduced sub-threshold slope and threshold-voltage variability when thinning the 2D material from three monolayers to one. This is an encouraging result, indicating that very thin channels are needed for further transistor scaling. For atom-thick channels, this work shows that the intrinsic variability is low, and comparable with silicon FinFETs. To make further progress in driving down device variability, so that it is suitable for future nodes, there needs to be better control of key process steps, like cleaning and contacts.

Figure 4. 1-2 monolayer MoS₂ FETs (with equivalent oxide thickness (EOT) =2.6nm) have higher threshold-voltage variability, but their slope approaches the silicon FinFET reference (EOT=0.8nm) (as presented at the 2020 IEDM conference).

Worldwide progress with 2D-FETs is positioning this class of transistor as a prime candidate for extending the logic device scaling roadmap. At imec, work by our team and our colleagues has started to lay the groundwork for introducing 2D semiconductors into a 300 mm integration flow – a key requirement for industrial adoption. We have already taken significant steps by improving device performance and developing a fundamental understanding of this form of FET.

This work is the result of a collaborative effort of a broad imec team working on exploratory logic.

References
Z. Ahmed et al. ‘Introducing 2D-FETs in device scaling roadmap using DTCO’ IEDM 2020.
K.K.H. Smithe et al., ‘Intrinsic electrical transport and performance projections of synthetic monolayer MoS2 devices’2D Materials 4 011009 (2017)
C-C Cheng et al. ‘First demonstration of 40 nm channel length top-gate WS_{2 p}FET using channel area-selective CVD growth directly on SiO_x/Si substrate’ 2019 Symposium on VLSI Technology Diest of Technical Papers.
D. Lin et al. ‘Dual gate synthetic WS₂ MOSFETs with 120 µS/µm Gm 2.7 µF/cm² capacitance and ambipolar channel’, IEDM 2020.
I. Asselberghs et al. ‘Wafer-scale integration of double gated WS2-transistors in 300 mm Si CMOS fab’, IEDM 2020.
Q. Smets et al. ‘Sources of variability in scaled MoS₂ FETs’, IEDM 2020.