CS Mantech: Optimal cocktails

A new era beckons, with better devices that draw on the strengths of the entire palette of compound semiconductors

BY RICHARD STEVENSON

Materials tend to be renowned for a particular asset. GaN is widely credited for handling very high power densities, InSb is known for its ability to allow carriers to zip around at high speeds, and HgCdTe is recognise for its capability to detect emission far into the infrared. Yet, for all these materials and more, alongside their strength comes at least one weakness.

Due to this, selecting any material involves compromise, with decisions weighing up what will enable the best overall device performance.

There is clearly much appeal in avoiding this limitation by selecting the optimal combination, rather than picking the best material. But that is far easier said than done, given that there are several tough challenges to overcome when uniting different families of compound semiconductor materials.

While these challenges may initially seem insurmountable, progress is being made, thanks to the toil of many researchers. Due to many different materials and technologies involved in these breakthroughs, it is hard to keep track of all the progress that’s being made. However, thanks to the extensive coverage on this topic at this year’s CS Mantech, held on 25-27 May, all the delegates attending this online meeting could gain a good grasp of the many advances being made to combine markedly different semiconducting materials, and how this success will impact the next generation of devices.

Setting the scene for how far we’ve come already and what the future may hold, Mark Rosker, the director of DARPA’s Microsystems Technology Office, opened the conference by outlining the three different eras for compound semiconductor devices. He views the first wave as that involving the production of devices on native substrates, such as GaAs-based MMICs; and the second as the growth of devices on foreign substrates – examples include GaN-on-SiC HEMTs, as well as antimonide-based structures, grown on GaAs and InP substrates, that form low-power, high-frequency electronic circuits. Rosker argued that a third wave is now starting to emerge, where devices feature abrupt junctions and high-performance materials with dissimilar lattice constants. “The fundamental technology that is being developed may be thought of as junction engineering,” explained Rosker. “Optimisation is happening at the level of the junction, in order to improve the overall device performance.”

To illustrate what a third-wave device might look like, Rosker highlighted a novel HBT pioneered by a collaboration led by researchers at the University of Wisconsin-Madison and Michigan State University. Using transfer of an AlGaAs/GaAs membrane grown on a native substrate, this team constructed a HBT with a diamond substrate, a p-type diamond collector, an Al₂O₃ intermediary layer and AlGaAs layers that provided the emitter and base junctions (see Figure 1). By employing a grafting technique, the engineers overcame a 37 percent lattice mismatch between the GaAs-based layers and diamond. It’s a breakthrough that unlocks the door to combining some of the traditional merits of a HBT with the excellent heat extraction of diamond, as well as its higher bandgap that boosts the transistor’s breakdown voltage.

Figure 1. Mark Rosker, director of DARPA’s Microsystems Technology Office, suggests that the compound semiconductor industry will soon enter a third wave of material technology. This era will see devices built from disparate materials.

One of the stepping stones towards a third wave of compound semiconductor devices has already been made in a DARPA programme. To address the speed-limiting high contact resistance in GaN HEMTs, efforts in the NEXT programme were directed at introducing the re-growth of heavily n-doped, lattice-matched GaN regions, inserted below the source and drain contacts. “The important point is not that you are using different materials – the important point is that you are starting to do junction engineering at levels that are below that of the entire device,” commented Rosker.

He also discussed ultra-wide bandgap materials, which he expects to make a significant impact in the next generation of devices. Merits of these materials, such as AlN, Ga₂O₃, diamond and BN, include a bandgap roughly twice that of GaN and an electric breakdown field that is higher by a factor of about four. However, there are weaknesses with these materials, with some difficult to p-dope and others lacking a substrate.

“The first issue, just as it was with the last generation, is to understand materials properties better, and to recognise what some of these material challenges are,” argued Rosker. According to him, accurate models of materials and their related devices are essential tools for aiding the understanding and development of this new class of compound semiconductors.

To help drive the third wave forward, DARPA has just started a heterogeneous heterostructures programme. In the first phase, the goal is to develop new processes for forming low-defect-density heterogenous heterojunctions.

The second part of the programme is focused on designing novel heterogenous heterostructures, underpinned by accurate physics-based modelling and simulation.

Releasable epilayers
A key process for producing the third wave of compound semiconductor devices is the growth of an epilayer, prior to its transfer to another material. Developing a very promising technology for accomplishing this is a group at MIT led by Jeehwan Kim, who provided an overview of a very broad portfolio of work on this topic to those attending this year’s CS Mantech.

It is well-known that lattice matching, a crucial requirement for the second wave of materials, restricts the options for combining materials, and may also lead to high wafer costs. But there are also two other significant weaknesses that must also be considered, according to Kim: due to the atomic spacing of the underlying substrate, the layers of the device may be “clamped”, and this could impair performance; and if the substrate cannot be released, it adds to weight while hampering flexibility.

Two of the most common options for releasing an epilayer are chemical and optical lift-off. The former is not ideal, as chemical treatment may degrade the quality of the substrate, hindering its re-use. “You have to polish your wafer after the release process,” explained Kim, pointing out that etching takes time, and is generally limited to III-V materials. The common alternative, optical lift-off, which involves directing laser emission through the back of transparent substrates to melt away material, also causes damage and takes considerable time – but it is quicker than chemical lift-off.

Figure 2. The approach pursued by Jeehwan Kim’s team at MIT enables substrate reuse by inserting a layer of graphene between the substrate (donor wafer) and an epilayer.

The novel approach pursued by Kim and his colleagues is to transfer graphene to a donor wafer, before adding an epilayer, applying a handle substrate, and then pulling apart this structure (see Figure 2). Thanks to the weak forces at the interface with graphene, there is a precise release of the epilayers from this carbon structure. Merits of this technique include: a fast release, due to the weak interaction; its application to any material; no need for any post-release treatment; and substrate re-use.

Table 1. engineers at Akash have many reasons for adopting a glass frit process when producing their GaN-on-diamond devices.

One of the merits of using a thin layer of graphene, rather than other two-dimensional materials, such as BN, is that it has a ‘transparency’ – that is, the ionic field penetrates through the carbon layer. Due to this, when epitaxy occurs, the deposited film is orientated to the underlying wafer. With this approach, Kim and his co-workers have formed single-crystalline, freestanding, flexible membranes of GaAs, InP, GaP and GaN, as well as a number of complex oxides, including SrTiO₃, CoFe₂O₄, Y₃Fe₅O₁₂ and BaTiO₃ (see Figure 3)

Figure 3. Jeehwan Kim’s team at MIT have used a technique referred to as remote epitaxy to grow a variety of thin films that are separated from the substrate. Apects of this work have been published in the following journals: Nature 544 340 (2017), Nature Materials 17 999 (2018), Nature Materials 18 550 (2019), Nature Electronics 2 439 (2019), Nature Nanotechnology 15 272 (2020), Nature 578 75 (2020)

The penetration of the ionic field through the graphene varies with material. With silicon it is weak, causing the growth of polycrystalline material. For GaAs it is a little stronger, so to produce crystalline films by remote epitaxy, graphene must be only a single layer thick; but for GaN, thanks to a relatively strong ionic field, remote epitaxy can yield crystalline films even when using two layers of graphene (see Figure 4).

Figure 4. For remote epitaxy, the penetration of the ionic field through graphene is key. For silicon, it’s so weak that subsequent growth produces polycrystalline material. With GaAs, the field is stronger, allowing crystalline growth through a single layer of graphene; and with GaN, the ionic field strength is so high that crystalline material can be formed with a double layer of graphene. More details on this work can be found in Nature Materials 17 999 (2018).

Kim and co-workers have also investigated heteroepitaxy, growing InGaP that has a lattice-mismatch to GaAs. Due to what Kim describes as spontaneous relaxation on graphene, there is a substantial reduction in dislocation density in the ternary compared with conventional epitaxy.

Virtues of this technology are not limited to producing flexible and stackable wafers and a reduction in material costs. There is also the promise of easy heterointegration, allowing stacking of different devices, such as III-V solar cells, wireless devices, processors and sensors, and batteries based on oxides.

While championing all of this opportunity, Kim is open about the challenges, which include compromises in epilayer quality associated with pinholes in graphene, possibly caused by the peeling process. He pointed out that it is important to use the right process to add the graphene layer. For producing compound semiconductor films, a wet process is unsuitable – there are imperfections in the morphology of graphene on its host substrate, such as a lack of perfect flatness, that impair the epilayer. A dry process is better, beginning with the formation of a layer of graphene on SiC.

One of the latest pieces of work by Kim’s team is to use its technology to form an artificial heterostructure containing blue, red and green LEDs. This stack of LEDs, which have lateral dimensions of several microns, is a promising candidate for making displays based on microLEDs.

Bonding wafers
A more established approach for bringing dissimilar compound semiconductor materials together is direct-wafer bonding. A variant of this, known as surface-activated bonding, has much appeal because it does not require any wet processing, with wafers bonded together at room temperature.

Figure 5. Working under vacuum, the bombardment of wafers with a fast atom beam (FAB) removes the native oxide, creating a surface for bonding.

To unite materials with this technique, wafers are loaded into a chamber that is pumped down to around 10^-6 Pa, before their surfaces are bombarded with beams of neutralised atoms, typically argon, that are accelerated by 1^-2 kV. These collisions eliminate native oxides and create activated surfaces. Pairs of wafers are then united by pressing them together, typically with a bond pressure of around 10 MPa (see Figure 5).

At this year’s CS Mantech, Naoteru Shigekawa, who is a group leader at Osaka City University and an expert in this form of wafer bonding, outlined the criteria for optimising this process, before illustrating its capability with examples of novel devices. While his facility is limited to bonding wafers up to 2 inches in diameter, he is quick to point out that there are commercial tools available, suited to high-throughput bonding of 300 mm wafers.

Shigekawa told conference attendees that the surface roughness of the wafers has an impact on bonding yield. Experiments by his team indicate that for successful bonding the surface roughness value Ra must be below 1 nm, and ideally less than half that value. Epiwafers tend to be well above this, but polishing flattens their surface, enabling successful bonding (see Figure 6).

Figure 6. The flatness of the wafers governs the bonding yield. Polishing reduces roughness, and increases the chances of a high-quality bond.

Care is needed when applying this form of bonding, because surface activation leads to dry etching, which can increase surface roughness and impair yield. Another downside of etching is that it introduces mid-gap states. “We assume that such mid-gap states have a negative impact on electrical properties of bonding interfaces,” stated Shigekawa, who added that one solution is post-bonding annealing, which can lead to the recovery of interface characteristics.

Illustrating this point, Shigekawa showed transmission electron microscopy of bonded silicon and GaAs wafers. Prior to annealing, there is an amorphous-like transition layer at the interface. Annealing at 300 °C causes this layer to shrink, and at 400 °C it disappears, thanks to recrystallisation.

Shigekawa and colleagues have also used electrical measurements to assess how annealing adjusts interfacial properties. Investigations of junctions formed by bonding two n-type silicon wafers together, and also by bonding two p-type silicon wafers together, showed that annealing at 1000 °C for 10 minutes drives down the density of interface states from around 1013 cm^-2 eV^-1 to one-fifth of this value.

The team from Osaka City University have produced a portfolio of novel devices with wafer bonding, including multi-junction solar cells, power devices with junctions between wide and narrow bandgap materials, and FETs that feature diamond layers to increase current spreading. For the latter, devices were formed by direct bonding of diamond to semiconducting materials – in once case silicon, and in another, GaAs – and also bonding diamond to a heat sink. The new architectures promise a substantial reduction in thermal resistance.

Figure 7. Compared to sapphire, diamond has a tremendously high thermal conductivity that drives down thermal resistance at this junction.

Using a thermal imager, Shigekawa and co-workers have measured the thermal resistance of their junctions. To provide a benchmark, they used a bonded GaAs-sapphire junction, which had a thermal resistance of 35 K/W (see Figure 7). In comparison, the GaAs-diamond junction has a resistance of just 6 K/W. This vastly superior value allows devices to be driven harder without overheating, or the adoption of simpler approaches to thermal management.

The researchers have also considered junctions formed by bonding GaN to diamond. Micro-Raman measurements on these structures, undertaken by Martin Kuball’s team at the University of Bristol, revealed that the stress within these structures is similar to that of GaN-on-silicon.

Diamond dissipation
At Akash Systems of San Francisco, CA, much effort has been devoted to developing GaN-on-diamond transistors, power amplifiers and radios for satellite communication. In this environment, the only mechanism for dissipating heat is radiation. With GaN-on-diamond, heat is drawn out of the channel of the HEMT far faster than with GaN-on-SiC, permitting a higher substrate temperature – and ultimately better heat extraction via radiation.

Note that avoiding high temperatures by driving the device less hard is not a great compromise, as this holds back the data transmission rates. Illustrating this point is one of Akash’s products, a GaN-on-diamond radio, which is accommodated in a 10 cm by 10 cm by 3 cm package, and when placed at an altitude of 550 km can delivers a date rate of more than 600 Mbit/s – that over five times the rate for conventional GaN-on-SiC technology at around 8 GHz, within a 100 MHz channel.

Those attending CS Mantech gained insights into the development of Akash’s GaN-on-diamond technology in a presentation by the company’s Vice President of Materials, Daniel Francis. He explained that many of the technical team are former founders and employees of Group4 Labs, which pioneered the technology. Progress in GaN-on-diamond continued after the acquisition by Element Six, and also after the launch of Akash, which bought-out the IP and introduced a production process on 100 mm wafers.

At Akash, engineers form devices by taking unprocessed GaN-on-silicon epiwafers, bonding a carrier to the epi-side, removing the substrate, growing a layer of diamond in its place, and then removing the temporary carrier. As the diamond that’s deposited forms a rather rough layer, this has to be polished.

Options for attaching the carrier to the epiwafer include diffusion bonding and plasma-activated bonding. But at Akash they prefer glass frit bonding – also known as glass soldering – for several reasons (see Table 1). The primary attributes of frit bonding are that it can be applied to a full wafer, it maintains its strength at the high temperatures subsequently employed for diamond growth, and it accommodates bow, warp and defects in the GaN.

Francis explained that by melting glass, they can cater for surface roughness and bow. “Because you make the glass thick enough, you can accommodate some level of roughness for defects that are five microns, without too much trouble.”



Akash, the pioneer of GaN-on-diamond, is producing 100 mm wafers in volume.

Working in partnership with Kuball’s team at Bristol University, the team at Akash have quantified the improvements in heat extraction that come from removing transition layers. These transition layers are hampered by their ternary nature, and also by the numerous defects (see Figure 8). Thermal conductivity is typically 15 W m^-1 K^-1, a value about ten times lower than that for GaN. To avoid this issue, Akash removes these transition layers, before adding diamond, which has a thermal conductivity of 1600 W m^-1 K^-1.

Figure 8. Akash uses GaN-on-silicon HEMTs as the starting point for the production of its GAN-on-diamond devices. Transmission electron microscopy images of GaN-on-silicon, showing a very high defect density in the transition layers (left), and GaN-on-diamond (right).

Depositing a high-quality layer of diamond on GaN is not easy. There is a tendency for diamond to attack GaN, leading to nanoscale structures that bare a resemblance to popcorn. The solution is to add a film of SiN. As this has a very low thermal conductivity, it needs to be as thin as possible, while still ensuring good-quality diamond films. A thickness of around 25 nm yields the best results, when considering both device performance and consistency, according to Francis.

As the deposited diamond forms grain that are tens of microns in size, polishing processes are needed to ensure a smooth surface. A first step reduces peak-to-valley variation from 30 mm to 5 mm, before a second step takes the surface roughness down to 0.5 mm . Applying both of these steps trims the total thickness of the diamond, which falls from around 200 µm to 105 µm.

Francis and co-workers have compared the performance of GaN-on-SiC HEMTs with those based on GaN-on-diamond. Measurements on the former, devices with a 150 nm gate length that operate at a frequency of 20 GHz and an efficiency of 25 percent, have a base plate temperature of 25 °C when the channel temperature is 200 °C. For the GaN-on-diamond variant, because the team is yet to perfect the 150 nm process, a gate length of 250 nm is employed. The larger gate drags down efficiency to 20 percent. However, encouragingly, the base plate temperature can be as high as 100 °C for a 200 °C channel temperature, allowing the device to operate up in space without the need for active cooling.

This promising result, like those of the devices described by Rosker – and those made at MIT and Osaka City University – provides a glimpse into the future of what will be possible. When devices draw on disparate materials, many doors could open, helping to elevate the importance of our industry to an entirely new level.