The allure of cubic SiC

The exceptional electronic and mechanical properties of the cubic form of SiC are enabling this polytype to take rapid strides towards serving in medical devices, MEMS and power electronic applications.

BY FRANCESCO LA VIA FROM THE INSTITUTE FOR MICROELECTRONICS AND MICROSYSTEMS

SiC is blessed with many attractive mechanical and electrical properties. Due to these attributes, it is a compelling candidate for making electronic devices and sensors that can be deployed in many settings. Chips made from SiC are strong contenders for deployment in sustainable energy systems, hybrid vehicles, low-power-loss inverters, implantable medical devices, optical devices, and in MEMS operating with high efficiencies at high temperatures.

One of the key considerations facing designers of SiC devices is which form of SiC is best for their target application. This wide bandgap semiconductor exists in nature in a number of crystalline structures, called polytypes, that are differentiated by the stacking sequence of the tetrahedrally bonded Si-C bilayers. Through variations in this stacking sequence, SiC adopts different atomic arrangements and symmetries, from hexagonal to cubic and rhombohedral – each has a different set of physical properties.

Today, the 4H form of SiC grabs the headlines, due to ramping volumes of diodes and MOSFETs for the electric vehicle market. Yet, despite all this success, it is not the best polytype in many important regards. This accolade could go to the cubic form of SiC, which has the highest electron mobility and saturation velocity, thanks to reduced phonon scattering that results from a higher symmetry. Known as 3C-SiC, this cubic polytype has the lowest bandgap – it is just 2.3 eV – and great thermodynamic stability, enabling growth at lower temperatures, such as less than 1500 °C.

Figure 1. Comparison between the channel mobility in 3C-SiC and 4H-SiC.

Unfortunately, thermodynamic stability at lower temperatures is actually a double-edged sword. Its downside is that it reduces the thermal budget required for growth, thus limiting development of a reliable 3C-SiC bulk growth technology for realization of the seed for subsequent homo-epitaxial growth of device-grade 3C-SiC epilayers. Due to the lack of such a substrate, device developers are forced to grow 3C-SiC hetero-epitaxially on different substrates. Much effort has focused on optimizing the hetero-epitaxial growth of 3C-SiC on the two common hexagonal polytypes, 6H- and 4H-, but manufacturing costs are prohibitively high.

With growth on a native substrate impractical, there is a strong desire from both a technological and a scientific perspective to be able to grow high-quality 3C-SiC epilayers on a substrate with as large an area as possible. Silicon is the obvious candidate: alongside its widespread availability, large sizes and high level of affordability, it can be grown by CVD, ensuring a very high purity of the resulting product.

Power devices
The capability of 3C-SiC for making power devices is illustrated in Table 1, which compares the electrical properties of this polytype to those of 4H- and 6H-SiC. Silicon is also included, for the sake of comparison. The excellent characteristics of 3C-SiC have fuelled a persistent interest by the research community – and supported by the power device industry – to develop 3C-SiC devices with breakdown voltages ranging from 600 V to 1.2 kV.

Table 1. The most relevant electrical properties of silicon, 3C-SiC, 6H-SiC and 4H-SiC.

Success would be most welcome. Growth on silicon would open the door to larger wafers and lower-cost production, while devices would benefit from high bulk electron mobilities, due to a higher symmetry within the crystal.

There are reports that channel mobility of 3C-SiC in structures produced with standard processing can reach ten times that of (0001) 4H-SiC (see Figure 1). Combined with the lower bandgap of 3C-SiC, the higher channel mobility should result in a lower value for on-state resistance, thereby reducing conduction losses in a forward-biased MOSFET. According to several device simulations, on-resistance should fall by about a factor of two, enabling a reduction in device area for the same on-resistance, and thus a lower-cost device.

Another attribute of 3C-SiC is its limited concentration of intrinsic carriers – they are about 11 orders of magnitude lower than that found in silicon. This tiny concentration, correlated to the band-gap of 2.3 eV, contributes to a lowering of device leakage current under reverse bias, even in the low-and medium-power regimes.

In addition to these strengths, 3C-SiC has a high thermal conductivity and excellent mechanical properties. These characteristics ensure that sensors and devices based on this polytype are capable of working at temperatures above 250 °C. Operating under such conditions is required for devices that run at very high powers, or in extreme environments, such as those found in hybrid-vehicle engines and aerospace turbine engines.

While there’s no doubt that 3C-SiC has much to offer, enabling this material to fulfil its promise is far from easy, due to many challenges associated with the development of high-performance devices. To facilitate marketable production of electronic devices material quality must improve, costs must fall, and there must be a substantial increase in wafer size. The hetero-epitaxy of 3C-SiC on silicon offers an ideal solution to the last two necessities, but if this growth process is to make a real difference to the chances of cubic SiC, there needs to be a fall in the density of crystallographic defects in the epilayer. These defects stem from the substantial difference in lattice parameters – they differ by 19 percent at room temperature – and the thermal expansion coefficients. For the latter, the difference between 3C-SiC and silicon is 23 percent at the deposition temperatures, and 8 percent at room temperature.

A variety of planar and volume defects originate at the interface between 3C-SiC and silicon. These defects include micro-twins, anti-phase boundaries and stacking faults in the epilayer, and voids in silicon beneath the hetero-interface (see Figure 2). These defects are device killers. However, their threat can be diminished by growing several tens of microns of 3C-SiC. This relatively thick film reduces their density, with some defects totally annihilated. Note that the defect density and the surface morphology strongly depend on the orientation of the silicon substrate.

Figure 2. Transmission electron microscopy cross-section of the interface between silicon and 3C-SiC. Several extended defects can be observed.

Over the past three decades much effort has been devoted to developing a process for bulk growth of 3C-SiC. The motivation for this is that in very thick layers it’s been observed that the defect density is low enough to enable the realization of power devices.

Working towards this goal is our team from the Institute of Microlectronics and Microsystems at Catania, Italy. We coordinated a four-year project entitled Challenge, which has driven the development of three different bulk processes that can produce a breakthrough in power technology.

Through collaboration, those of us involved in this European project have developed a process for the bulk growth of 3C-SiC. Seeds of this polytype are formed on silicon (100) substrates that are loaded into a horizontal hot-wall CVD reactor, prior to the growth of epilayers with a thickness of 70 µm. A subsequent increase in temperature beyond the melting point of silicon (see Figure 3 for a temperature profile of the process) causes this substrate to fully melt inside the CVD reactor. The remaining freestanding SiC layer can then be employed as a seed layer for homoepitaxial growth, using a low-pressure regime and different temperatures (between 1600 °C and 1700 °C).

Our team increased substrate thickness with two hours of growth at a rate of 60 µm/h, with the last 10 µm low-doped for device realization. With this approach, using nitrogen and aluminium to form both n-type and p-type layers, our team produced 3C-SiC homoepitaxial samples with a thickness of about 200 µm, and wafers with diameters of 100 mm and 150 mm (see Figure 3).

Figure 3. Temperature schematics of the CVD process for the bulk growth of 3C-SiC. 100 mm and a 150 mm wafers are reported too.

Using this methodology, we have reduced the density of stacking faults with respect to thin layers by two orders of magnitude to typically just 10² cm^-1. Measurements of several p-n junctions formed by this approach show reasonable characteristics (see Figure 4). The leakage current of the diodes is still high, so efforts must be directed at a further decrease in the defect density, so that 3C power devices can deliver a competitive performance compared with their 4H cousins in the range of breakdown voltages between 600 V and 1200 V.

Making MEMS
The 3C form of SiC is blessed with very good mechanical properties (see Table 2). They include a high Young’s modulus, a high fracture and flexural strength, and a low density. Thanks to the high ratio between Young’s modulus and the density, devices made from 3C-SiC have exceptional promise for realizing very robust MEMS that can work at high frequencies. What’s more, these MEMS can operate at very high temperatures, such as 600 °C, because even in this regime there is not a large reduction in Young’s modulus.

Figure 4. Forward (a) and reverse (b) characteristics of 3C-SiC p⁺/n junctions on a bulk wafer grown by CVD. While the forward characteristics are almost ideal, the reverse show a high leakage current, due to the high defect density.

Efforts at developing micro- and nano-mechanical resonators have been motivated by the wide range of applications they can serve, both in industry and supporting fundamental science. These resonators can be used for precision sensing of mass, and to measure ultrasound, magnetic fields, inertia and strain. For many of these applications it is essential to realise a high resonator quality factor.

Recently, remarkable progress has been made in improving the quality factor of micro- and nano-mechanical resonators that are fabricated from highly stressed, thin amorphous films – most particularly amorphous SiN – formed on a silicon substrate. Further progress is possible by switching from these amorphous films to crystalline materials, which offer a range of advantages that could deliver a step-change in performance. One of the merits of high-purity crystalline materials is their comparatively low defect density that allows significantly higher intrinsic quality factors. Values for this figure-of-merit of above 10⁵ have been reported for highly pure diamond, CaF, and 3C-SiC – and when surface losses are eliminated, quality factors can exceed 10⁶. This value far exceeds the quality factor of 25,000 for amorphous SiN and 1,000 for amorphous silicon. What’s more, crystal-lattice mismatch is a benefit rather than a curse, as crystalline material with a high intrinsic stress is better suited to dissipation dilution.

Table 2. Physical properties of silicon, SiC and diamond.

Yet despite these significant advantages, thin-film crystalline resonators are still to demonstrate the dramatic improvements in quality that have been shown in their amorphous counterparts. Progress is partly impaired by the increased complexity of fabrication, and – when grown on a silicon substrate – the dislocations and the high density of stacking faults near the interface. These imperfections degrade the mechanical quality factor and the Young’s modulus.

In the last few years much progress has been made with 3C-SiC MEMS, due to developments in the growth process, in processing and in design. Several projects have reported success, including one we have coordinated called SiC nano for picoGeo. By addressing many of the potential pitfalls, this European effort has realised extremely good materials properties, even for films with a thickness close to 1 μm (see Figure 5).

Figure 5. (up) Double clamp beam array with different lengths and widths. (left) An increase in the Young’s modulus with increasing thickness is observed in both (100) and (111) 3C-SiC. (right) The Q-factor increase at high residual stress is essentially in (111) 3C-SiC. In (100) 3C-SiC, the residual stress is lower, as is the Q-factor.

Our measurements of the Q factor in structures with identical dimensions and design show that for the (111) form of 3C-SiC there is a clear linear dependence on residual stress, while this dependence is not clear for the (100) variant. Due to this characteristic, we are able to produce very efficient resonators, extremely sensitive strain meters and other high-performing MEMS devices with (111) 3C-SiC.

In the SiC nano for picoGeo project our team has produced a very sensitive strain meter, capable of detecting in the 10^-12 -10^-13 range. Such a high degree of sensitivity enables this sensor to detect very small deformations that occur a few hours before the eruption of a volcano or before an earthquake. These strain meters could also measure the deformation of a dam or a bridge.

It’s worth noting that when 3C-SiC is used to make MEMS, only a thin layer of this material is needed, due to its good mechanical characteristics. Thanks to this, the fabrication process is quite easy, as it involves etching a thin layer of SiC, prior to a deeper etch of the silicon substrate, which can be accomplished using the standard process for silicon MEMS.

Implantable medical devices
Another important application where 3C-SiC can make a valuable contribution is in implantable medical devices. Silicon is highly toxic, leading researchers to pursue new classes of composite semiconductors, such as 3C-SiC, that offer a healthier solution. Experimental work by several groups suggests that SiC is extremely biocompatible, and is a good choice for this kind of device (see Figure 6).

Within the family of SiC poltypes, 3C-SiC appears to be a better option than its hexagonal siblings, because it enables the realization of thin implantable devices by etching the silicon substrate. This approach has enabled the fabrication of a neural probe (see Figure 6).

Figure 6. (left) Cell proliferation for silicon and SiC. (right) A SiC neural probe.

This work is in its infancy, and there are still issues to overcome. The biggest of these is the high leakage current from the junctions used to isolate the device from the substrate. Once this problem is overcome, 3C-SiC could be used to produce neural probes for the medical sector.

The cubic form of SiC clearly has much promise for power devices, MEMS and medical devices. Over the last few years much progress has been made in improving the structural quality of this material so that it can begin to fulfil its potential for delivering an outstanding performance. Thanks to these advances, it’s not long before we could start to see the first commercial 3C-SiC devices on the market.


Further reading http://h2020challenge.eu/http://picogeo.eu/