Gate to the future

Reliability benefits from deploying deposited gate oxides in SiC MOSFETs.

BY ARNE BENJAMIN RENZ, PETER GAMMON, OLIVER VAVASOUR, VISHAL SHAH AND MARC WALKER FROM THE UNIVERSITY OF WARWICK, SUPPORTED BY JAMES GOTT FROM WARWICK MANUFACTURING GROUP AND ANDREW NEWTON AND MICHAEL POWELL FROM OXFORD INSTRUMENTS PLASMA TECHNOLOGY

The potential of wide bandgap power devices to deliver efficient, compact and light power conversion has been known since the 1980s. However, it was not until the late 2010s that the first SiC power converters from Tesla, BYD, Hyundai and others demonstrated the reliability and viability of the material for mass adoption. In the wide bandgap boom that followed, numerous press releases from OEMs and IDMs announced SiC chip supply agreements and joint ventures. In turn, multiple SiC IDMs have announced major billion-dollar expansion plans and supply agreements from SiC substrate manufacturers. The result is an industry that is predicted by Yole to reach $8.9 billion in 2028 at an average compound annual growth rate of 31 percent.

Figure 1. Individual series resistance contributions to total specific on-resistance in 650 V and 1200 V planar MOSFETs.

With a SiC MOSFET based inverter expected to be 5 percent more efficient than a silicon IGBT equivalent, the fact that the SiC chips can be up to three times more expensive is more than compensated for by the potential battery reduction. However, as OEMs become more familiar with the technology, and competition between SiC IDMs mount, so the pressure for cost reductions increase. This is fuelling the development and adoption of 200 mm diameter substrates, the move to automated fabrication, and a move to reuse substrates.

However, many of the tools of cost reduction sit with the device designer, for whom every milliohm of resistance in their design contributes to the size of the finished die. By minimising the specific resistance of a die, a given product will be smaller, in turn increasing yields. As such each of the yields shown in Figure 1 need to be minimised, including the MOSFET channel, which is the subject of this work.

Figure 2. (left) Cross-sectional image emphasising the individual resistance contributions and (middle and right) an image of a packaged device.

Challenges in gate structures
With up to one third of a SiC MOSFET’s resistance originating from the channel, shown in Figure 2, this is one of the dominant resistance components in 650 V or 1200 V MOSFETs for EV systems. The main reason for this highly resistive channel is the high density of defect states at the interface between the semiconductor and dielectric. For the SiO₂/SiC interface, the density of interface defect states is typically between a hundred and a thousand times higher than it is for SiO₂/silicon. These unwanted states, and the charges trapped in them, enhance scattering at the interface. In turn, the increased scattering drags down channel mobility and significantly increases the channel resistance. The channel mobility in today’s commercial MOSFET applications is just 20-40 cm² V^-1 s^-1, far lower than the theoretically achievable bulk mobility of SiC, which is around 1000 cm² V^-1 s^-1.

Ironically, the root cause of the high channel resistance in the SiC MOSFET is related to one of its biggest strengths: unlike GaN and diamond, SiC can be thermally oxidised to form SiO₂. However, the presence of carbon causes problems.

Figure 3. (Top) Interface states build-up due to incomplete carbon transfer away from the interface and (middle) interfacial charge scattering in the channel, causing a decrease in channel mobility; (bottom) common post-oxidation anneals to improve channel mobilities.

During regular oxidation, occurring at temperatures of more than 1200 °C, SiO₂ initially forms through the consumption of SiC, and carbon is dispersed as CO₂. However, as the SiO₂ get thicker, not all carbon can diffuse through it, causing carbon to accumulate at the SiC/SiO₂ interface (see Figure 3). This trapped carbon creates charge states in the channel region of the SiC MOSFET that scatter electrons and impair the channel mobility of this transistor.

One option for improving channel mobility is post-oxidation annealing in NO or N₂O. Alternatively, the oxide can be grown using NO or N₂O directly. The origin for this improvement is disputed, but a popular and widely accepted explanation is that the nitrogen attaches itself to dangling bonds and other atomic defects, rendering them passive and inactive. Of the two sources of nitrogen, NO gives the highest channel mobility. However, as it is toxic and difficult to handle safely, N₂O is often used instead.