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Technical Insight

Magazine Feature
This article was originally featured in the edition:
Volume 30 Issue 6

Bipolar p-FETs enable all-GaN power integration

News

Bipolar transport overcomes the inherent barriers of GaN p-FETs to pave the way to higher current densities.

BY MENGYUAN HUA FROM SOUTHERN UNIVERSITY OF SCIENCE AND TECHNOLOGY

GaN power devices have many attributes. They are renowned for their exceptional switching efficiency and high power density, strengths that are driving the development of miniaturised, energy-saving power systems. Thanks to a wide bandgap and stable material properties, GaN-based power devices are also capable of maintaining a good performance in challenging environments, such as extreme temperatures and irradiation conditions. And in addition to these capabilities, GaN power devices are revolutionising power systems towards higher levels of integration and intelligence. Given all this, it’s of no surprise that GaN-based HEMTs have rapidly surpassed traditional silicon devices to play an indispensable role in a number of fields, ranging from consumer electronics to industrial power supplies.


Figure 1. A promising option for GaN integration is the combination of the p-GaN gate HEMT and the bipolar p-FET.

However, while much progress has been made to date, there is still much more to do. In this regard, one important area for improvement is the GaN power IC – today there is a significant challenge in realising the seamless integration of power devices with low-voltage peripheral circuits. In the latest approaches to hybrid integration, the silicon-based circuits that are used for driving, sensing and protecting functions, are integrated with GaN power devices through packaging. This results in non-negligible parasitic inductance, which can lead to gate ringing, particularly during high-power fast-switching transients. Two downsides of this are a limited switching speed and a compromised system reliability. What’s more, the silicon devices in these hybrid designs fail to handle extreme environments as well as GaN devices, narrowing the application scope. Consequently, moving to an all-GaN integration strategy has much appeal, including liberation from parasitic issues and the constraints of silicon-based devices, as well as the opportunity to unleash the full potential of GaN power ICs.

There are several straightforward approaches for all-GaN integration, such as leveraging established n-channel device technology, resistor-transistor logic and direct-coupled FET logic. However, all these methods are impaired by excessive power consumption, due to a significant static current that diminishes the efficiency of the power IC and necessitates enhanced heat dissipation strategies.

A promising solution to effectively blocking the static current is the GaN-based complementary logic IC, incorporating both the p-FET and the n-FET. In this design, the existing p-GaN layer on the E-mode GaN HEMT platform is used to fabricate the p-FET.


Figure 2. (a) An n-p-n epi-structure on the conventional p-GaN HEMT platform and a secondary ion mass spectrometry depth profile of magnesium and silicon dopants. Atomic force microscopy images of the (b) initial p-GaN surface and (c) GaN surface after n-p-n stack growth on the E-mode GaN HEMT platform.

The simplicity of this approach has attracted much attention, leading to efforts directed at boosting p-FET performance via strategies that include reducing interface trap states, downscaling the device, and engineering the gate dielectric. But even with these refinements, the current density of the p-FET falls far short of that of the GaN HEMT. This gap in current density between the GaN p-FET and its n-FET sibling poses a significant hurdle for progressing GaN CMOS technology.

Limiting the current density of the GaN p-FET is the low conductivity of the p-GaN layer. Due to a considerable effective mass and strong scattering, the mobility of holes is nearly two orders of magnitude lower than it is for electrons. Compounding this issue, magnesium is the only effective dopant available for p-type GaN. Unfortunately, it’s far from an ideal dopant, being held back by a low activation ratio and a deep energy level that restricts the hole concentration in the p-GaN layer to 1018 cm-3. While innovative epi-structure designs involving N-polar GaN, AlN and GaN heterostructures, superlattices, and InGaN insert layers are able to enhance hole mobility or density, these approaches are incompatible with the existing commercial p-GaN gate HEMT platform.