News Article

Strained Silicon Joins The Drive To Keep CMOS Chips On Course

The huge costs of scaling CMOS devices according to Moore's Law have left the silicon industry at a crossroads. Mayank Bulsara of AmberWave Systems describes how strained silicon technology will be able to push performance further without the need for big investment.
The 30 year run of the semiconductor industry has been driven by the tremendous scientific and manufacturing work that has centered on Si CMOS technology. The technological improvements of CMOS chips are best exemplified by Moore s Law, which essentially predicts that transistor size scales down every 18 months, allowing for greater performance per transistor and increased transistor packing density. Both of these factors provide greater functionality in CMOS chips, which is beneficial to the consumer.

An implicit foundation of Moore s Law is that the performance benefits and technological innovations do not cost more than consumers are willing to pay (i.e. the economics of CMOS scaling must make sense). For 30 years the use of transistor scaling as the provider of greater system performance, without other significant perturbations in CMOS manufacturing, has made a variety of companies in the Si industry incredibly successful. However, the economics of CMOS scaling are no longer valid for many industry leaders. This is evidenced by the narrowing of gross margins, limited growth in such mainstay semiconductor industries as the PC microprocessor industry, and the increasing number of new joint ventures - with their associated cost-sharing models - for the construction of next-generation fabs.New materials, higher performancePerhaps the most telltale sign of the changing Si industry is that new materials are being taken seriously as replacements for SiO2 as a gate dielectric and isolation layer, for Al as a metallization layer, and for Si as a base substrate. These materials are required to continue the steady progression of CMOS technology. The most interesting and long reaching of these material changes involves the Si substrate itself. Si has been the workhorse of the semiconductor industry for some time, but its fundamental properties in terms of carrier mobility and associated intrinsic performance are limited. These limitations are now being exposed for various applications and the base Si substrate material is being replaced for some devices.

Silicon-on-insulator (SOI), which improves chip performance via capacitance reduction, has been introduced in products and is on the roadmap of most major Si chip companies. Single-isotope Si substrates with improved thermal conductivity are becoming relevant for highly integrated CMOS chips where heat dissipation is a concern. Going to the greatest extreme, integrated III-V devices on Si substrates have created tremendous interest, even though the direct application of such technologies may not take place for many years.

On the immediate horizon, one of the most promising alternatives for the replacement of bulk Si substrates in the CMOS industry is strained Si technology.

Strained Si technology enables improvements in CMOS performance and functionality via replacement of the bulk, cubic-crystal Si substrate with a Si substrate that contains a tetragonally distorted, biaxially strained Si thin film at the surface. Due to changes in its crystalline structure (i.e. its symmetry is different due to its strain state), the strained Si film has electronic properties that are superior to those of bulk Si. Specifically, the strained Si film has greater electron and hole mobilities, which translate into greater drive current capabilities for NMOS and PMOS transistors, respectively. This increased transistor drive current can be traded off for a reduction of dynamic power consumption.

The ability to tailor the performance of strained Si technology for each specific application will have a far-reaching impact, from high-speed products like microprocessors and field-programmable gate arrays, to the low-power products used in wireless communications and other mobile devices.Strained Si fabricationThe key to enabling high-performance devices is the fabrication of a low-defect-density strained Si film. Growing a Si layer on a SiGe film, which has a larger lattice constant than Si, generates the strained Si heterostructure. The challenge faced when forming this heterostructure is the engineering of the lattice constant of the SiGe film. Done improperly, the SiGe film can be very defective and the subsequent strained Si film will inherit the defect morphology of the underlying SiGe. The development of SiGe relaxed graded-layer technology by Eugene Fitzgerald of MIT provided an effective method for engineering the lattice constant of the SiGe film, and produced the first demonstration of high electron mobility in strained Si heterostructures (Fitzgerald et al.).

The sequence for fabrication of a strained Si heterostructure involves three steps. First a SiGe relaxed graded layer is formed to engineer the lattice constant of the SiGe alloy. The relaxed SiGe graded layer is an epitaxial thin film with a sequence of layers that have a gradually increasing Ge content (typically the profile is linear) up to a final Ge composition. Next a constant composition Ge film is grown to spatially separate the subsequent strained Si film from the misfit dislocations that are intentionally introduced in the SiGe relaxed graded layer. The final step is the deposition of the Si film, which is placed in a state of biaxial tension as it conforms to the lattice of the constant-composition SiGe layer. Figure 1 shows a schematic of the basic elements of a strained Si heterostructure.

Once a low-defect-density SiGe film can be fabricated, the strained Si heterostructures can be tailored to enable various properties. One of the key determining factors for the performance enhancement available with strained Si technology is the amount of strain imparted to the strained Si thin film, which is determined by the Ge content in the underlying SiGe film.

Figure 2 shows that the electron- and hole-mobility enhancements increase with increasing strain (Currie et al., Leitz et al.). Using a higher Ge fraction in the underlying SiGe layer increases the degree of strain in the Si. It should be noted that various reports have erroneously implied that strained Si does not provide hole-mobility/PMOS device enhancements. In fact, hole-mobility enhancement in strained Si has a more complicated behavior, but can extend beyond the electron-mobility enhancement achievable in strained Si if enough strain is imparted to the film.

Although working with higher Ge content in the SiGe layer increases the performance characteristics of the NMOS and PMOS transistors, the tradeoff is that the strained Si film needs to be thinner due to critical thickness constraints. Thus, the engineering of strained Si heterostructures with higher Ge content provides less latitude for substrate manufacturing and, as will be discussed later, device processing.Substrate supplyStrained Si technology provides great performance benefits for CMOS, but as with any new technology that is introduced to a manufacturing infrastructure, the ease with which it is adopted is very dependent on the number and severity of changes the new technology requires. In tandem, the manufacturing cost of the technology determines its rate of acceptance in the industry.

For strained Si technology, the key question for many manufacturers is whether the substrate technology can be taken from research laboratories, which typically use UHV epitaxy techniques, to large-scale production, which requires high throughput, low-cost techniques. Strained Si processes have now been demonstrated and devices have been produced using industry-standard low-pressure Si epitaxy systems, such as the ASM Epsilon and Applied Materials Epi Centura platforms, and unique systems still under development such as the Aixtron G3 platform.

Although epitaxy and SiGe graded-layer processes are at the core of strained Si technology, the manufacturability of devices is largely dependent on a proprietary chemical-mechanical polishing (CMP) process introduced between the epitaxy of the relaxed SiGe buffer layer and the strained Si.

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