CMOS gets ready for high-speed wireless LANs
An example of this is clearly demonstrated by researchers at Toshiba (Fujimoto et al.) who have developed a 7.0 GHz CMOS LNA exhibiting an NF of only 1.8 dB. Even in the Si world many still feel that a BJT offers superior performance to that of a MOSFET device, though most would concede that a CMOS device will be more cost-effective than a BJT. However, for LNAs, specifically when they are used in the front end of a WLAN receiver, minimizing noise is critical to the overall performance of the device. The main noise sources in MOSFETs are due to the thermal noise of the channel and the gate resistance. Advanced MOSFET processing, using low-resistance salicided gates, eliminates the gate-resistance issue, leaving thermal noise in the channel as the primary noise source.
In the case of the BJT, the noise sources are the thermal noise due to base resistance and the shot noise of the collector current. Unfortunately for the BJT, these noise sources are not independently controllable. Base resistance can be decreased by using larger geometries, but this requires more collector current to maintain a high ft, which in turn causes more shot noise in the collector. Therefore, one source of noise is typically traded off for another, making it very difficult to reduce the overall noise characteristic. Because of this limitation in BJTs, the Toshiba researchers believe that a CMOS approach is technically superior to that of a Si BJT, and so have focused on this device for 802.11a WLAN applications. Noise reduction The parasitic resistance exhibited by the lossy Si substrate at high frequencies not only consumes signal power, but also generates thermal noise. The methods used to minimize this effect include the use of SOI substrates, as well as high-resistivity Si substrates. While both methods improve RF performance, they also increase the manufacturing costs, reducing one of the major advantages of using CMOS in the first place.
Rather than utilizing substrate modifications to reduce noise, the Toshiba researchers have combined a standard 0.25 µm CMOS approach with two noise-reducing design modifications. The first uses a cascode configuration implemented with a dual-gate MOSFET. In a MOSFET structure, a parasitic diode exists at both the source and drain, causing signal loss into the Si substrate as well as a volume in which thermal noise can be generated. Using the dual-gate approach, where the area represented by the drain of the first MOSFET is shared by the area represented by the source of the second MOSFET, the effect is to reduce the overall area of the parasitic diodes (when compared with using two single-gate MOSFETs), and therefore the overall noise. Circuit simulations comparing the dual-gate to the single-gate approach indicate that the dual-gate-based LNA attains 1.2 dB higher gain and a significant 0.7 dB lower NF. Pad shielding The second modification made to reduce noise and to improve output power is to shield the pads of the device. It was observed that under 7 GHz operation the Q of the inductors, which were fabricated in low-resistivity thick metal above relatively thick insulating layers, had a value of 10. The pads, which are almost directly on the Si substrate (with a thin isolating layer beneath them), had a Q value of 5, indicating much greater coupling to the substrate.
In order to eliminate this effect a shielded pad approach was implemented, in which an isolated metal layer encapsulated with CVD SiO2 is placed beneath the pad and grounded (see figure). This shield completely isolates the pad above it from the Si substrate. The shielded pad approach improved gain by 4 dB and reduced noise by another 0.8 dB.
When both of these design modifications were implemented, the resulting 7 GHz LNA, operating with a 2.0 V power supply and consuming 6.9 mA of power, showed an increased output power of 5.2 dB and a reduction in NF of 1.5 dB. This resulted in a device with an overall gain of 8.9 dB and a NF of 1.8 dB. Such characteristics make this device more than suitable for WLAN applications at 5-6 GHz, and because it is fabricated in a basic CMOS process, with the only real processing change being the shielded pads, it will be able to maintain low processing costs. This combination of low cost and high performance represents very strong competition to any III-V solution in the rapidly growing WLAN market, and clearly demonstrates that CMOS can be a real player in the 5-6 GHz regime. Further reading Fujimoto et al. 2002 J. Solid State Circuits 37(7) 852.
