Soitec strengthens R&D partnership with LETI
Under the terms of the Smart Cut-Enabling Application Laboratory (SCEALAB) partnership, Soitec and LETI will enhance their existing collaborative R&D efforts. Also, Soitec will gain exclusive rights to LETI s intellectual property relating to Smart Cut technology - including full sub-licensing rights to the technology - to target applications beyond silicon and SOI substrates.
Smart Cut is a process used to transfer ultra-thin silicon layers from a handle wafer to another surface. During SOI wafer manufacturing using the Smart Cut process, a silicon wafer is oxidized, implanted with hydrogen ions and bonded to a second Si wafer. The wafers are then separated along the cleavage plane formed by the implanted ion, leaving an SOI substrate and a reusable Si wafer.
The extension of Smart Cut technology to new composite-material substrates is now well under way. According to Carlos Mazure, Soitec s chief technology officer, Smart Cut technology enables more efficient and optimized use of expensive compound material wafers. As a result, Soitec will be able to offer a broad range of new materials related to silicon, silicon carbide, silicon germanium, sapphire and III-V materials.
"Innovation has always been the driving force behind Soitec s development efforts, which have included testing and evaluating new materials for tomorrow s markets," said Mazure. "This extended partnership with LETI gives us access to an already established state-of-the-art infrastructure and proven analytical tools, providing us with significant time-to-market advantages."
Under the extended agreement, SCEALAB R&D activity will be conducted in LETI s facilities, as well as in Soitec s new, state-of-the-art R&D facility in Bernin, France. The R&D facility s work will encompass a number of key applications to further extend the company s proprietary Smart Cut technology used for manufacturing next-generation material substrates.
Researchers at Soitec s new state-of-the-art R&D facility will focus on the development of strained SOI and silicon-on-quartz (SOQ) substrates (developed in conjunction with Soitec licensee, Seiko Epson). In addition, Soitec plans to use the facility to further extend its current SOI wafer product portfolio. Soitec s R&D facility features a Class 1, eight-inch cleanroom totaling approximately 6,000 square feet.
