Fujitsu sets transistor speed record
In IEEE Electron Device Letters (Vol. 23, No. 10), Akira Endo and colleagues at Fujitsu, in collaboration with researchers at Osaka University and the Communications Research Laboratory in Tokyo, described the fabrication methods used to make the 25 nm gate length device.
The layers were grown by MOCVD onto a semi-insulating InP substrate. The In0.7Ga0.3As channel was grown onto a 300 nm thick InAlAs buffer layer. The key to achieving the high-speed performance lies in fabricating a device with a high In content in the channel and the correct channel aspect ratio.
Achieving the best aspect ratio requires that the channel layer thickness and the distance between the gate electrode and the channel must be as small as possible to avoid a marked increase in the short channel effect that can affect the performance of devices with such low gate lengths.
The group were able to do this using what is described as a 2-step recessed gate technique that reduced the gate electrode-channel distance to just 4 nm. The source-drain spacing was 2 µm and the Ti/Pt/Au Schottky T-gate was 50x2 µm wide and 25 nm long. The processing was also done at low-temperature (below 260 C) to reduce fluorine contamination.
Hall measurements at room temperature showed that the 2DEG mobility was 10,000 cm2Vs. The maximum drain-source current was 0.8 A/mm at a Vgs of 0.4 V. The pinch off voltage was –0.45 V and the off-state breakdown voltage was below –1V. The extrapolated ft was 562 GHz and fmax was 330 GHz.
While such devices are some way from being manufacturable in any large volume they may eventually find use in future generations of optical communications at 160 Gbit/s and also for mm-and sub-mm wave applications.
