New on-wafer testing concepts accelerate VCSEL production
Infineon Technologies, for instance, is a leading supplier of VCSELs for parallel optical applications. Infineon s PAROLI product at 850 nm is now commercially available in high volume, and 1.3 µm VCSELs for medium-reach applications are to be commercialized soon (Schmale et al.).
VCSELs offer particularly strong advantages in both fabrication and test. This is mainly due to the fact that testing can be carried out at the wafer stage. In contrast, competing edge-emitting lasers have to undergo costly "back-end" procedures - including cleaving, coating and bonding - where significant yield reduction occurs before test and qualification steps can be carried out.
The most fundamental and common test that is carried out for semiconductor laser devices is the determination of light-current-voltage (LIV) characteristics over the typical current range of the device. The collected LIV data is analyzed by linear regression to determine laser threshold, slope efficiency, knee voltage and series resistance, as shown in figure 1.
High-volume production and testing of optoelectronic components such as VCSELs and LEDs makes it necessary to migrate from the typical laboratory research equipment used in many industrial fabs towards high-throughput test equipment. As an example of the difficulties faced, a single 4 inch GaAs wafer contains around 100,000 individual VCSELs, all of which need to be analyzed with high accuracy.
Accelerated test procedures
The availability of advanced testing technologies that are compatible with standard PC peripherals provides highly economical ultra-fast testing concepts that were until now only available for the high-budget applications associated with traditional silicon manufacturing.
A new laser diode source measurement module and optical power module has recently been introduced by Irish company PXIT. It has been designed to help photonic component manufacturers minimize their overheads, and is now being utilized by Infineon Technologies for VCSEL testing.
Infineon has evaluated PXIT s test equipment, in combination with a Süss PA-200 automatic wafer test stage, and has investigated the acceleration of test procedures and the concept of test-head duplication.
Figure 2 shows how the timing restrictions arise in typical wafer test cycles. Three different test configurations are compared. Figure 2a shows a traditional approach using GPIB instruments (see "GPIB and PCI" box) and single device-under-test (DUT) contacting cycles. The two other timing curves refer to the use of the PXIT test equipment applied in a single DUT contacting cycle (figure 2b), and a parallel multi-DUT contacting cycle (figure 2c).
The most severe timing constant is the contact cycle of the wafer handler (the time to move from one device on the wafer to the next in simple configurations). A typical figure is about 750 ms, due to the fact that the equipment has to incorporate and balance heavy loads such as components for RF and temperature shielding. The testing and sensing equipment also has to be adjusted with high accuracy.
After the contact cycle, typical testing procedures start with a verification of contact integrity. This is usually accomplished by a resistance check across Kelvin contact pairs applied in all testing applications to remove the parasitic resistance caused by system wiring and probe-needle contacting. Once this is verified as being within tolerance, the LIV scan can begin.
For VCSEL devices it is typical to run a scan of 100 points from 0 to 10 mA in 0.1 mA steps. At each drive current step, the voltage drop across the diode is measured and stored locally. The optical power emitted from the VCSEL chip is also collected by a photodiode and stored by the test system.
The overall test time for a typical 2 inch VCSEL wafer containing 20,000 devices adds up to around 11 h (at 2 s per device) for the traditional approach using GPIB and single-DUT contacting. The challenge is to make significant improvements on this time.
