Wafer bonding brings SOI to strained silicon devices

It was inevitable that these two significant enhancements would be brought together in a single process, and it should come as little surprise that researchers at IBM s Watson Research Center, who have performed extensive work in both these areas, have merged them into a single process (Huang et al.).

Bonding beats implantation

SOI wafers are typically made in one of two ways, either through separation by implanted oxygen (SIMOX) or wafer bonding. During the SIMOX process a high-dose oxygen implant is performed, and through subsequent high-temperature annealing (in excess of 1000 °C) a buried oxide layer is formed beneath the surface Si layer. While this process has served standard SOI applications well, it has proved very difficult to incorporate in the presence of a SiGe buffer layer above the implanted oxygen. Problems arise during the high-temperature annealing step required to form the buried SiO2, in which it is difficult to maintain the integrity of the SiGe/Si layers. As a result, the IBM researchers have combined the SOI and strained Si processes by using wafer bonding.

The process flow is illustrated in the figure. A strain-relaxed SiGe buffer layer with uniform Ge content in the range of 15-25% above a step-graded SiGe layer is first grown by UHVCVD. Surface smoothness is critical to successful wafer bonding. Due to the relaxation of the SiGe layer during the step grade, the resulting surface is cross-hatched. To provide the required low roughness for wafer bonding, a chemical-mechanical polishing (CMP) process is used to reduce the roughness from an as grown 6-8 nm RMS to about 0.5 nm RMS. A high-dose hydrogen implant is performed with the ion energy selected to place the implant peak within the lower portion of the SiGe buffer.

The polished SiGe wafer is then bonded to a Si handle wafer, which has a 300 nm thermal oxide layer on its surface. The bond between the two wafers is formed by a 20-30 h anneal at a temperature of 250-350 °C. Once the bond has been formed, a second higher temperature anneal (400-500 °C) induces a splitting process that separates the bonded wafer pair along the hydrogen implant peak. This results in an approximately 500 nm thick relaxed SiGe layer along with the 300 nm buried oxide atop the Si handle wafer.

A second CMP process is then performed to smooth the SiGe surface, which is left roughened by the hydrogen splitting process. This is followed by UHVCVD growth of a second thin layer of SiGe with the same Ge mole fraction as the transferred SiGe buffer, followed by the deposition of 18 nm of strained Si.

Both NMOS and PMOS devices were fabricated in the strained Si layer using gate oxides of 4 nm and channel lengths of 25-250 µm. Similar devices were fabricated on Si-only control substrates in order to make performance comparisons. The NMOS devices were fabricated on SiGe buffers with a Ge content of 15%. Drain current comparisons with the Si-only control devices extrapolated to give a 50% higher effective electron mobility in the strained SOI devices. The Si universal mobility curves taken at an effective field of 1.0 MV/cm also showed 50% greater mobility in the strained SOI devices.

In the case of the PMOS devices, a larger Ge content (20-25%) is needed as the mobility enhancements are not as strong as in the NMOS devices. Mobility improvements in the range of 15-20% were observed over the Si-only devices for effective fields of 0.2-0.5 MV/cm. A fall off in this enhancement is seen at higher effective fields, as is observed in conventional strained Si PMOS devices.

These results clearly show that the incorporation of a buried oxide into the strained Si process flow results in significant enhancements over the Si-only approach, and minimal degradation of the enhancements normally provided by the strained Si process. While no RF measurements were reported, it would be expected that the typical RF improvements observed in an SOI CMOS processes would also be obtained here.

Lessons from the III-V experience

This process clearly has the potential to produce the best possible RF performance of any CMOS process, but as has been learned time and time again in the III-V community, no-one is willing to pay extra for performance that they do not need.

So while this process offers obvious performance benefits, they do come at a significant process cost: two starting substrate wafers, two UHVCVD growth sequences, two CMP sequences, a high-dose hydrogen implant, and a long annealing time. This process will undoubtedly be able to produce III-V-like device results, but the low costs that are normally associated with CMOS will not apply to this strained SOI CMOS process. In the end, it may be costs rather than performance that determine the commercial viability of this approach.

Further reading

Huang et al. 2002 Trans. Elec. Dev. 49(9) 1566.