Wafer-scale processing leads to low-cost optical integration
Clearly, too few similarities exist between the silicon semiconductor industry and emergent photonics. While silicon manufacturers build systems-on-a-chip, photonics manufacturing is bogged down at the breadboard stage of assembly and functionality. The billion-dollar question is how can the photonics industry achieve a silicon-like economy of scale and a level of automation that will provide the dense, functional modules necessary to propel it forward technically and financially?
For photonics the fundamental problem is that non-silicon-based compound semiconductor material systems must be used to perform the required optical functions. An example is a 1R receiver; this device requires a photodiode to detect the appropriate wavelength and a transimpedance amplifier (TIA) to amplify and convert the photo-generated current to a usable voltage for the system. The photodiode for C- and L-band networks is comprised of an InP-based pin photodiode, while the TIA can be silicon, GaAs or even SiGe. Receiver module manufacturers purchase and/or manufacture photodiodes and TIA chips separately, and then practice hybrid assembly techniques to complete the module (see figure 1a).
These sub-assemblies add large parasitics that limit the bandwidth of the components to less than 15 GHz, and make them very costly to produce. Moving forward, photonic devices are expected to operate at up to 40 Gbit/s and it is obvious that the current form of photonic component manufacturing is inadequate. Some photonic component companies are scrambling for a solution to combine optical functions with electronic components as efficiently and cost-effectively as possible. Others are simply stepping away from the business.
Wafer-level integration Efficient integration of components offers a way to increase network system functionality and reduce the manufacturing costs of these highly integrated components. To achieve component integration, manufacturers are implementing two main methodologies: monolithic and hybrid. The monolithic approach uses a single material system to fabricate several components together on a common substrate, hence it has limited flexibility. The material system chosen must be able to support electronic circuitry and also emit, detect and guide light of the proper wavelength. Each element or sub-component must be designed and optimized as a collective unit in a material system that may not be the best choice for that component, leading to inevitable design compromises.
The hybrid approach relies on the assembly of sub-components that have been optimized independently in their own material system; however, current hybridization techniques impose limits on physical size and on electrical performance, and suffer from high manufacturing costs.
Wafer-level heterogeneous integration technology is essential to fully harness the potential of high-performance optoelectronic components and the manufacture of cost-effective sub-modules for next-generation communication networks. However, although the advantages are obvious, the methodology has so far been elusive.
Optogration, a start-up company based in Newburyport, MA, has developed a proprietary, wafer-scale integration technique that enables the direct fabrication of optical devices on foundry-processed semiconductor wafers. The technique is called epitaxial layer transfer (ELT), and allows the integration of an entire unprocessed epitaxial wafer containing optoelectronic structures such as LEDs, lasers or photodiodes with any application-specific circuit or array of circuits. Subsequently, devices or circuits are fabricated directly on the host wafer using standard photolithography.
Figure 2 illustrates the basic concept of the ELT process. In this example, an InGaAs-based photodiode epiwafer on an InP substrate is bonded to a circuit wafer using a proprietary bonding layer. The InP substrate is then removed, and the epilayer patterned and processed, creating photodiodes in precisely defined areas of the underlying circuit wafer. Unwanted epitaxial material between the photodiodes is removed. The photodiode structures are individually isolated, thereby reducing all resistive, capacitive and inductive parasitics between the devices (passive or active) and the circuit.
The transferred epilayer is thin and semi-transparent, allowing precise alignment of the optical device to the host circuit. The size and alignment of the optical devices is limited only by lithographic constraints. This approach varies significantly from other wafer-bonding techniques, such as those used to manufacture CdHgTe detector arrays, where detectors must be fabricated on the host wafer prior to bump-bonding to a silicon read-out (RO) IC. Therefore precise alignment of the two wafers becomes problematic as dimensions decrease.
Commercial devices To demonstrate the advantages of our technology, a fully functional 320 x 256 passive imaging receiver was fabricated with 25 µm square pixels on a 30 µm pitch (see figure 3). This receiver was fabricated with the ELT process by integrating high-speed InGaAs MSM photodiodes with an off-the-shelf silicon ROIC manufactured by Indigo Systems (part #ISC9705). Figure 4 shows an image from a first-generation receiver, illustrating the successful integration to a commercial ROIC. It demonstrates that the technology is adaptable to commercial circuits and that costly circuit redesigns are not necessary for circuit manufacturers to utilize the process.
Optogration has also integrated InGaAs pin photodiodes and avalanche photodiodes with arrays of silicon- and GaAs-based TIAs for optical networking systems. A 10 Gbit/s TIA with a transimpedance of 1000 Ω is currently in manufacturing, with beta testing scheduled for the first quarter of 2003. The design utilizes a fully depleted 0.18 µm SOI process for the TIA, chosen for its high-frequency operation, high yield and low cost. A discrete design, and 4 x 4, 2 x 16 and 2 x 32 arrays, will be delivered from manufacturing in early 2003.
Figure 1b shows a photoreceiver utilizing ELT integration. Compared with the hybrid assembly in figure 1a, this integrated device does not contain a submount or wire bonds, which add to manufacturing costs. To our knowledge this will be the first fully integrated pin-TIA receiver array made with fully depleted SOI technology capable of 10 Gbit/s per channel operating in the C and L bands.
Future integration We view compound semiconductor integration as a packaging problem at the sub-wafer level. Heterogeneous integration technology is essential to fully harness the potential of high-performance optoelectronic components and the cost-effective manufacture of sub-modules for next-generation communication networks. The ELT process and the current implementations illustrate the vitality of this technique as an effective manufacturing tool across the compound semiconductor technology spectrum. We have demonstrated that the technique is capable of integrating devices as small as 7 µm per side and as large as 100 µm per side with silicon and GaAs ICs. Our demonstrations have initially focused on integrating optical detectors and electrical circuits, however, ELT has the potential to affect a much broader range of optoelectronic components. Going forward, we envision ELT as an enabling technology that offers the photonics industry a truly cost-effective and manufacturable method of delivering highly integrated OEICs with system-on-a-chip functionality.
