Technical Insight
Strained Si-on-insulator development accelerates
With strained Si now on the CMOS roadmap and wafer bonding accepted as a method for producing SOI substrates, Gianni Taraschi looks at the ongoing efforts to combine the two technologies.
Recently, a number of semiconductor manufacturers have announced plans to incorporate strained Si into future CMOS technologies, yielding enhanced performance for minimal additional cost. Typically, the strain in a thin Si surface layer is induced by a SiGe graded buffer deposited onto a Si substrate. Tensile strain significantly increases carrier mobility, thereby improving performance (Compound Semiconductor September 2002 p39). Another material that has been used for some time now in CMOS fabrication is Si-on-insulator (SOI). In SOI, a buried insulating oxide layer reduces parasitic junction capacitance, thereby increasing drive currents while decreasing noise and power dissipation.
There has been rapid progress in the development of process technologies that merge both strained Si and SOI. To achieve this end, processes typically involve the creation of engineered substrates consisting of relaxed SiGe-on-insulator (SGOI), which serve as templates for thin strained Si layers. Due to the presence of the surface strained Si and the underlying buried oxide, the final structure is sometimes referred to as strained Si-on-insulator (SSOI).
Separation by implanted oxygen (SIMOX) and wafer bonding are popular approaches
for the fabrication of a buried oxide. SIMOX involves the implantation of oxygen ions
into the wafer surface, followed by a high-temperature anneal to remove implant damage from the crystalline layer and form the buried oxide layer. Although ideal for bulk Si, SIMOX has been unsuccessful when applied to SiGe with Ge contents above 30%, due to thermal instability during high-temperature post-implant annealing (Compound Semiconductor November 2002 p37).
In contrast, wafer-bonding approaches do not suffer from this limitation, and allow for SGOI substrate fabrication with any Ge content, in addition to strained Si directly on oxide. For this reason, a number of groups in both industry and academia have developed high-quality SGOI and SSOI substrate fabrication based on wafer bonding. All of these methods begin with the growth of a relaxed SiGe graded buffer on a Si substrate, which minimizes the density of dislocations in the surface film. The SiGe graded buffer then serves as the donor for the bonding process, but each method employs different techniques to achieve smooth transferred layers.
The Si stop-layer approach
A first demonstration of SGOI fabrication using wafer bonding was presented at the 2000 Electronic Materials Conference (Taraschi et al. 2002a). Via the use of a strained Si etch stop layer, the process ensures that the final structure possesses a smooth and uniform SiGe film, with a RMS roughness of about 1 nm. Figure 1 shows the process flow, beginning with the growth of a relaxed SiGe buffer, graded up to the desired surface Ge content. Due to the influence of dislocation strain fields during growth, the surface of the SiGe buffer is considerably roughened and requires polishing to provide a flat surface for subsequent growth steps and wafer bonding. After polishing, a strained Si etch-stop layer followed by about 100 nm of SiGe is deposited onto the graded buffer (figure 1a). The wafer is then bonded to an oxidized Si handle wafer (figure 1b), the backside of the original wafer is ground away, and a selective etch (KOH or TMAH) removes excess Si while stopping in the SiGe graded buffer (figure 1c). KOH and TMAH solutions have been shown to quickly etch Si while effectively stopping on SiGe with Ge content greater than 20%, making these etchants ideal for a backside removal process.
Next, excess SiGe is removed using one of the many selective SiGe etchants that stop on the strained Si layer (figure 1d). Numerous chemical etchants containing hydrogen peroxide, nitric acid or ammonia can be tailored to etch SiGe at a much faster rate than Si, and are therefore ideal for selective etching. Once the process is complete, the final structure consists of a strained Si layer on a uniform thickness SiGe layer bonded to a buried oxide.
There has been rapid progress in the development of process technologies that merge both strained Si and SOI. To achieve this end, processes typically involve the creation of engineered substrates consisting of relaxed SiGe-on-insulator (SGOI), which serve as templates for thin strained Si layers. Due to the presence of the surface strained Si and the underlying buried oxide, the final structure is sometimes referred to as strained Si-on-insulator (SSOI).
Separation by implanted oxygen (SIMOX) and wafer bonding are popular approaches
for the fabrication of a buried oxide. SIMOX involves the implantation of oxygen ions
into the wafer surface, followed by a high-temperature anneal to remove implant damage from the crystalline layer and form the buried oxide layer. Although ideal for bulk Si, SIMOX has been unsuccessful when applied to SiGe with Ge contents above 30%, due to thermal instability during high-temperature post-implant annealing (Compound Semiconductor November 2002 p37).
In contrast, wafer-bonding approaches do not suffer from this limitation, and allow for SGOI substrate fabrication with any Ge content, in addition to strained Si directly on oxide. For this reason, a number of groups in both industry and academia have developed high-quality SGOI and SSOI substrate fabrication based on wafer bonding. All of these methods begin with the growth of a relaxed SiGe graded buffer on a Si substrate, which minimizes the density of dislocations in the surface film. The SiGe graded buffer then serves as the donor for the bonding process, but each method employs different techniques to achieve smooth transferred layers.
The Si stop-layer approach
A first demonstration of SGOI fabrication using wafer bonding was presented at the 2000 Electronic Materials Conference (Taraschi et al. 2002a). Via the use of a strained Si etch stop layer, the process ensures that the final structure possesses a smooth and uniform SiGe film, with a RMS roughness of about 1 nm. Figure 1 shows the process flow, beginning with the growth of a relaxed SiGe buffer, graded up to the desired surface Ge content. Due to the influence of dislocation strain fields during growth, the surface of the SiGe buffer is considerably roughened and requires polishing to provide a flat surface for subsequent growth steps and wafer bonding. After polishing, a strained Si etch-stop layer followed by about 100 nm of SiGe is deposited onto the graded buffer (figure 1a). The wafer is then bonded to an oxidized Si handle wafer (figure 1b), the backside of the original wafer is ground away, and a selective etch (KOH or TMAH) removes excess Si while stopping in the SiGe graded buffer (figure 1c). KOH and TMAH solutions have been shown to quickly etch Si while effectively stopping on SiGe with Ge content greater than 20%, making these etchants ideal for a backside removal process.
Next, excess SiGe is removed using one of the many selective SiGe etchants that stop on the strained Si layer (figure 1d). Numerous chemical etchants containing hydrogen peroxide, nitric acid or ammonia can be tailored to etch SiGe at a much faster rate than Si, and are therefore ideal for selective etching. Once the process is complete, the final structure consists of a strained Si layer on a uniform thickness SiGe layer bonded to a buried oxide.
