Photoresist application for 3D features on wafer surfaces
For most wafer lithography process steps, spin-coated liquid photoresist (LPR) is utilized, and for wafer surfaces with little topography this results in a layer of fairly uniform thickness. However, because the uniformity of the spin-coated LPR layer depends heavily on the topography of the wafer surface and the properties of the photoresist (viscosity and vapor pressure), this technology can fail dramatically in the coverage of highly elevated or deeply etched structures. Effects include severe resist thinning on mesa sidewalls and the tops of elevated features, and deep puddle formation within deeply etched via holes as shown in figure 1. In extreme cases the LPR may "skip over" or "tent" via holes without filling them.
Electrophoretic photoresistTo overcome the limitations of using spin-coated, solvent-based LPR on wafer surfaces with extreme 3D topography, electrophoretic photoresist (EPR) has been recently introduced to wafer fabrication. EPR has been used by the printed circuit board industry for several years, and it has enabled conformal photoresist coverage on highly irregular-shaped surfaces such as via holes. This technology is now being used for semiconductor and MEMS fabrication (Paine et al. 2002; Klocke et al. 2002). The EPR deposition process is very similar to electroplating, and requires a thin conducting seed layer on the wafer surface. The process consists of three steps: electrophoresis, electrolysis and electro-osmosis.
After the wafer is immersed in an aqueous emulsion containing the EPR, a high voltage is applied between the conductive seed layer and a counter electrode for several seconds. This results in the deposition of a highly conformal resist layer onto the seed layer as shown in figure 1. Since the resist layer is insulating, the current decreases rapidly as the resist layer thickness increases, until a self-limiting thickness is reached when the current drops to zero.
M/A-COM has two distinct wafer processing applications where conformal masking of high-topography surfaces is desired. The first application involves a silicon-on-glass (SOG) device technology that requires conformal masking of retrograde profiles up to 170 µm high (Chinoy et al. 1994). The second application is for GaAs wafer through substrate via holes. For high-power GaAs devices, a solder-stop metal needs to be masked inside the via holes to prevent Au-Sn eutectic solder from wicking into the holes during the solder die attach step (Hendriks et al. 2001, 2002). For low aspect ratio via holes on 100 µm thick GaAs wafers, a high-viscosity, positive thick LPR has been successfully used for several years. However, smaller via holes with increased aspect ratios and reduced diameters are desired for shrinking device die size, so LPR may no longer be able to fulfill this application.
HMIC silicon pedestal structuresFigure 2 shows 170 µm high silicon pedestal structures, which are an integral part of the heterolithic microwave integrated circuit (HMIC) process. A highly conductive layer has to be deposited over the pedestal region. Sputter-deposited TiW/Ag/TiW satisfies the requirements, since sputtered films tend to give sufficient coverage and Ag has excellent conductivity. Selective removal of the sputtered film from the top center of the pedestal region is desired, so a conformal resist mask is required in order to protect the metal films on the pedestal top perimeter edge, sidewalls and base during the subsequent wet etch step. The silicon pedestals can be fabricated utilizing a wet, anisotropic etch process, which results in sidewalls parallel to (111) planes and 55º sidewall angles, or an inductively coupled plasma etch, which produces slightly retrograde sidewall profiles.
Wafers with pedestals fabricated using the wet, anisotropic etch process were sent from M/A-COM to Semitool Inc for coating with PEPR 2400 photoresist. This is a positive EPR from Shipley Company that contains negatively charged micelles. Micelles are colloidal particles containing the active resist constituents, including the polymer, photoactive compound, solvents and dye. The PEPR 2400 was deposited in a Semitool semiautomatic, single-wafer electrochemical deposition (ECD) platform fitted with an EPR reactor. The deposition parameters, such as temperature, filtration, voltage, current and the PEPR 2400 TC plasticizer concentration, were maintained at Semitool s process of record conditions. After deposition the wafers were baked on a hotplate at about 100 ºC for 10 min to remove moisture from the film and smooth the film surface. Conformal PEPR 2400 coatings over the 170 µm high pedestals covered with the TiW/Ag/TiW layers were achieved for all of the wafers.
Figure 3 shows SEM images of the resist layer with excellent uniform coverage over the underlying structures. Smooth, continuous coverage of resist film was achieved over all of the analyzed features. About 70% of the average thickness was maintained over even the most challenging feature, a square-topped plateau with sharp outside corners. Typical coverage over convex corners is slightly thinner than the average thickness because of rounding that occurred during the bake step.
Alignment and exposure were done using a Canon PLA-501F broadband contact/proximity mask aligner. A tetra-methyl ammonium hydroxide (TMAH)-based developer solution was utilized, and this step was followed by an oxygen plasma descum. The wafers were then subjected to a TiW wet etch composed of hydrogen peroxide and ethylene diamine tetra-acetic acid (EDTA) at room temperature (RT), but this etch did not initiate. Subsequent Auger surface and depth analysis showed strong signals for Ti and O at and near the sputtered film surface. Titanium oxidizes more readily than tungsten, and the surface of the Ti layer was anodized during the EPR deposition process. In this case oxidation of the seed layer occurred in addition to the electrolysis reaction. A buffered oxide wet etch removed the Ti oxide layer, so that the TiW etch solution could be subsequently used after a quick de-ionized water rinse. The Ag was also etched by the RT hydroxide peroxide/EDTA solution.
GaAs through substrate via holesFor high-power GaAs devices, a positive photoresist mask is used to cover solder-stop metal inside the via holes while this metal is wet-etched from the backside, leaving a gold surface for subsequent Au-Sn eutectic solder die attach. The oxidized metal solder-stop lining the via hole sidewalls prevents the Au-Sn eutectic solder preform from wicking into the hole during die attach. The holes can be up to 100 µm deep, as shown in figure 4. Recently, there has been a strong effort to reduce the via hole size and increase the aspect ratio, which can result in coverage problems when using LPR (Hendriks et al. 2002). EPR can be used to achieve continuous, conformal coverage.
GaAs wafers were mounted on sapphire carriers utilizing a temporary thermoplastic bonding adhesive and thinned to 100 µm. Through substrate via holes (figure 4) were fabricated using reactive ion etching, and a Ni/Au/Ni metal stack was blanket-deposited onto the backside surface and via holes using electrodepostion. PEPR 2400 was deposited onto the electroless Ni solder-stop layer (anode) utilizing the Semitool Equinox ECD platform with the wafer holder adapted for the thicker sapphire carriers. During deposition the thin wafer and carriers were rotated to improve uniformity and prevent gas generated during the electrolysis reaction from becoming trapped inside the via holes. After deposition the samples were baked on a hotplate as previously described. Figure 5a shows the PEPR 2400 coverage of the wafer backside surface and via holes after the hotplate bake step. Backside dice streets on the wafers were defined using a Karl Suss MA-150 backside contact aligner (i-line) for exposure. The wafers were then immersed in TMAH-based developer solution and descummed in an oxygen plasma barrel asher. A Tencor P-11 surface depth profiler was used to measure the resist thickness at five points (near the major and minor flats, the wafer center, and opposite the major and minor flats) across several of the wafers on the backside surface using the open dice streets. The average resist thickness per wafer ranged from 9.5 to 10.5 µm with a total thickness range across an individual wafer of approximately 3 µm.
After descum, the Ni was removed from the dice streets using an RT, dilute ferric chloride wet etch as shown in figure 5. The gold was then removed from the dice streets using a RT potassium iodide/iodine-based etch solution. Both etch solutions were compatible with the PEPR resist mask. A second backside contact alignment, expose, develop and descum process sequence step was used to remove the resist from the backside surface, while leaving the via hole sidewalls covered. The backside nickel was removed using the same ferric chloride wet etch. A thin layer of gold from a gold sulfite bath was plated onto the etched surface to improve wettability to the Au-Sn eutectic solder preform (Hendriks et al. 2001). Finally, the PEPR was stripped from within the via holes, leaving behind an oxidized nickel lining.
Integration of EPR into the wafer fabThe cost of a tool to deposit EPR onto wafer surfaces utilizing a conductive seed layer is comparable to the cost of a LPR spin coat and hotplate bake module. The deposition time for EPR may be slightly less than for spin coating, so wafer throughput may be higher depending on the comparison of specific platforms. A conventional contact and proximity mask aligner can be used for exposing the EPR masks. The develop and strip chemistries are very similar to those already utilized in most wafer facilities. The PEPR 2400 positive resist mask is compatible with most wet-etch chemistries used to pattern metal films on wafers. The major advantage of EPR over LPR masks for wafer processing is its ability to give continuous, conformal coverage over large 3D structures.
Further readingD Paine et al. 2002 NEPCON West Conf. Proc. 265.
J Klocke et al. 2002 Pan Pacific Symp. Conf. Proc. (SMTA) 35.
P Chinoy et al. 1994 IEEE MTT-S Digest 1137.
H Hendriks et al. 2001 Compound Semiconductor October p85.
H Hendriks et al. 2002 GaAs MANTECH Conf. 105.
