Technical Insight
GaN HFETs on silicon target wireless infrastructure market
The high breakdown voltages inherent in GaN HFET technology make it well suited to high-voltage operation in wireless infrastructure applications, according to Ricardo Borges, Jeff Brown, Allen Hanson, Sameer Singhal, Andrei Vescan and Paul Williams of Nitronex Corporation.
The material properties of GaN have long been considered ideal for high-power microwave applications. Having developed a proprietary process, designated SIGANTIC, for growing GaN on silicon, Nitronex has created the opportunity to exploit the material properties of GaN while benefiting from the wide availability, high quality and low cost of silicon substrates.
However, the real proof of a semiconductor s capability is seen in its application to a commercial situation, prompting Nitronex to consider a number of markets in its search for a match for the properties of GaN. This has led to the development of a prototype power transistor for the UMTS or third-generation (3G) power-amplifier market.
RF power transistors for 3G
Wireless infrastructure RF power-transistor technology has evolved as new air-interface standards demand increasingly higher performance. Second-generation cellular networks based on the GSM standard use constant envelope modulation. The amplifiers needed to boost these signals can be effectively built with current silicon and GaAs technologies. Capitalizing on its lower substrate and overall process cost, silicon-based technologies gained the lion s share of the market, with the more recent LDMOS process surpassing the older BJT technology. Only in Japan did GaAs MESFETs and HFETs manage to keep a stronghold in the market.
Emerging 3G standards such as W-CDMA use variable-amplitude envelope modulation, which places much stricter constraints on the linearity of the power amplifier (PA) to minimize distortion. This in turn demands a more linear power transistor, so LDMOS manufacturers continue to upgrade their transistors, with the leading vendor now working on a fifth-generation process. The emphasis is on maximizing efficiency at a given level of linearity. In the race to squeeze more performance from existing technologies, process development teams are beginning to encounter the limits posed by the fundamental properties of the underlying semiconductor material.
Transistor requirements
The transistor linearity is commonly expressed in terms of the adjacent channel power ratio (ACPR). As the name implies, the ACPR is a measure of the amount of power spilling into the adjacent channels referenced to the power in the transmit channel. A typical set of RF power transistor requirements addressing the 3G power-amplifier market is shown in table 1.
To achieve the required linearity, W-CDMA transistors must operate with the power backed off to well below their peak capability. For example, a state-of-the-art LDMOS transistor with a P1dB rating of 180 W is capable of producing about 38 W (~80 mW/mm) of linear power under W-CDMA modulation, at 28 V operation. Constrained by a device technology of moderate power density, LDMOS manufacturers must utilize very large gate peripheries and correspondingly very low die impedances to keep scaling up the power. As that happens, the bandwidth of the matching circuit is reduced. With lower operating voltages (12-15 V), higher operating currents and lower thermal conductivity than silicon, GaAs HFET manufacturers face an even more challenging task than their silicon counterparts.
These issues can be circumvented by a higher power density technology, which enables higher total output power and increased bandwidth resulting from a more compact layout. In the case of GaN HFETs, their high-frequency response can also address higher-frequency bands, as future generations of wireless systems push up in frequency, while their inherent higher-voltage capability can open up new PA architecture and system options. Certainly, these attributes should not come at the expense of the superior linearity and efficiency demanded from present and future RF power transistors, as will be discussed in the following sections.
GaN on silicon
One of the major challenges of GaN technology is the material growth, and intrinsically linked to it is the choice of the substrate material. For the foreseeable future, bulk GaN will not be available in practical sizes, or at a reasonable price. Therefore, the focus is still on the more conventional substrates - sapphire, SiC and silicon. Of these, silicon has been shown to be the most difficult substrate to grow on, especially due to its more than 50% lower thermal expansion coefficient.
The tensile stress upon cooling down from growth temperature presents a significant challenge towards achieving high-quality epitaxial layers. However, several groups (Krost and Dadgar 2002) have developed transition layers or stress-compensating buffer layers, enabling the growth of thick, crack-free GaN layers on silicon. In particular, Nitronex s SIGANTIC process, employing a proprietary (Al,Ga)N transition layer, has demonstrated the ability to reproducibly grow thick, crack-free GaN layers on silicon with excellent electrical transport properties (Rajagopal et al. 2002). This process was initially developed on a 2 inch platform, and then successfully transferred to a 100 mm GaN HFET pilot line in the fourth quarter of 2001.
It is true that the issues related to growing good-quality material in spite of the significant lattice and thermal expansion coefficient mismatch have been addressed, and workable solutions are available for each of the mentioned substrates. The final choice of substrate is not a question of feasibility, but rather of the targeted application, in conjunction with economical aspects such as volume and cost.
Sapphire substrates, although available at moderate costs and large substrate sizes, present a challenge in the thermal design of power devices given their low thermal conductivity. Process steps intended to mitigate the thermal limitations, such as aggressive thinning or flip-chip mounting, increase cost and complexity. On the other hand, while SiC has excellent thermal conductivity, large-area substrates with low defect density are not yet commercially available. It remains to be seen whether these highly priced substrates will be competitive for commercial applications.
Using silicon as a substrate material enables a variety of commercial applications and manufacturing technologies. On a 100 mm platform, standard silicon packaging techniques, as one example, can be used to bring this state-of-the-art compound semiconductor to production volumes.
However, the real proof of a semiconductor s capability is seen in its application to a commercial situation, prompting Nitronex to consider a number of markets in its search for a match for the properties of GaN. This has led to the development of a prototype power transistor for the UMTS or third-generation (3G) power-amplifier market.
RF power transistors for 3G
Wireless infrastructure RF power-transistor technology has evolved as new air-interface standards demand increasingly higher performance. Second-generation cellular networks based on the GSM standard use constant envelope modulation. The amplifiers needed to boost these signals can be effectively built with current silicon and GaAs technologies. Capitalizing on its lower substrate and overall process cost, silicon-based technologies gained the lion s share of the market, with the more recent LDMOS process surpassing the older BJT technology. Only in Japan did GaAs MESFETs and HFETs manage to keep a stronghold in the market.
Emerging 3G standards such as W-CDMA use variable-amplitude envelope modulation, which places much stricter constraints on the linearity of the power amplifier (PA) to minimize distortion. This in turn demands a more linear power transistor, so LDMOS manufacturers continue to upgrade their transistors, with the leading vendor now working on a fifth-generation process. The emphasis is on maximizing efficiency at a given level of linearity. In the race to squeeze more performance from existing technologies, process development teams are beginning to encounter the limits posed by the fundamental properties of the underlying semiconductor material.
Transistor requirements
The transistor linearity is commonly expressed in terms of the adjacent channel power ratio (ACPR). As the name implies, the ACPR is a measure of the amount of power spilling into the adjacent channels referenced to the power in the transmit channel. A typical set of RF power transistor requirements addressing the 3G power-amplifier market is shown in table 1.
To achieve the required linearity, W-CDMA transistors must operate with the power backed off to well below their peak capability. For example, a state-of-the-art LDMOS transistor with a P1dB rating of 180 W is capable of producing about 38 W (~80 mW/mm) of linear power under W-CDMA modulation, at 28 V operation. Constrained by a device technology of moderate power density, LDMOS manufacturers must utilize very large gate peripheries and correspondingly very low die impedances to keep scaling up the power. As that happens, the bandwidth of the matching circuit is reduced. With lower operating voltages (12-15 V), higher operating currents and lower thermal conductivity than silicon, GaAs HFET manufacturers face an even more challenging task than their silicon counterparts.
These issues can be circumvented by a higher power density technology, which enables higher total output power and increased bandwidth resulting from a more compact layout. In the case of GaN HFETs, their high-frequency response can also address higher-frequency bands, as future generations of wireless systems push up in frequency, while their inherent higher-voltage capability can open up new PA architecture and system options. Certainly, these attributes should not come at the expense of the superior linearity and efficiency demanded from present and future RF power transistors, as will be discussed in the following sections.
GaN on silicon
One of the major challenges of GaN technology is the material growth, and intrinsically linked to it is the choice of the substrate material. For the foreseeable future, bulk GaN will not be available in practical sizes, or at a reasonable price. Therefore, the focus is still on the more conventional substrates - sapphire, SiC and silicon. Of these, silicon has been shown to be the most difficult substrate to grow on, especially due to its more than 50% lower thermal expansion coefficient.
The tensile stress upon cooling down from growth temperature presents a significant challenge towards achieving high-quality epitaxial layers. However, several groups (Krost and Dadgar 2002) have developed transition layers or stress-compensating buffer layers, enabling the growth of thick, crack-free GaN layers on silicon. In particular, Nitronex s SIGANTIC process, employing a proprietary (Al,Ga)N transition layer, has demonstrated the ability to reproducibly grow thick, crack-free GaN layers on silicon with excellent electrical transport properties (Rajagopal et al. 2002). This process was initially developed on a 2 inch platform, and then successfully transferred to a 100 mm GaN HFET pilot line in the fourth quarter of 2001.
It is true that the issues related to growing good-quality material in spite of the significant lattice and thermal expansion coefficient mismatch have been addressed, and workable solutions are available for each of the mentioned substrates. The final choice of substrate is not a question of feasibility, but rather of the targeted application, in conjunction with economical aspects such as volume and cost.
Sapphire substrates, although available at moderate costs and large substrate sizes, present a challenge in the thermal design of power devices given their low thermal conductivity. Process steps intended to mitigate the thermal limitations, such as aggressive thinning or flip-chip mounting, increase cost and complexity. On the other hand, while SiC has excellent thermal conductivity, large-area substrates with low defect density are not yet commercially available. It remains to be seen whether these highly priced substrates will be competitive for commercial applications.
Using silicon as a substrate material enables a variety of commercial applications and manufacturing technologies. On a 100 mm platform, standard silicon packaging techniques, as one example, can be used to bring this state-of-the-art compound semiconductor to production volumes.
