Technical Insight
Epitaxy and the high-κ dielectric contest
The race is on to find a replacement for SiO2 as a gate dielectric in CMOS. Jörg Osten describes the challenges faced, and how knowledge from III-V materials science will help.
Device miniaturization has been the primary means by which the semiconductor industry has achieved the unprecedented gains in productivity and performance known as Moore s Law. These gains have historically been paced by the development of new optical lithography tools, masks and photoresist materials. Now, a new challenge has appeared on the horizon that will require considerable resources to overcome. If not addressed, this could result in a major showstopper for the silicon industry (Green et al. 2001). The challenge is the replacement of the traditional SiO2 gate dielectric by new high dielectric constant (high-κ) materials. Meeting this challenge may require the CMOS industry to draw upon technologies such as epitaxial deposition and characterization techniques developed by the compound semiconductor industry. Such technologies are already being used for other new materials, such as strained Si/Ge alloys, which are now being developed.
The gate dielectric problemSiO2 has been used as the primary gate dielectric material in field-effect devices since the beginning, and the thickness of SiO2 films has decreased with each device generation. Table 1 shows the timeline for the anticipated future size reduction and the required oxide thickness. In a production environment it is very difficult to obtain oxides thinner than 8-10 Å as will be required in the next 5 years.
One of the fundamental limits to the scaling of the gate dielectric is the exponential increase in tunnel current with decreasing film thickness. For SiO2, at a gate bias of ~1 V, the leakage current changes from ~10-6 A/cm2 at ~3 nm to ~10 A/cm2 at ~1.5 nm - seven orders of magnitude in current for a thickness change of only a factor of 2. A high gate leakage current can conceivably alter device performance, to say nothing of the difficulties associated with power consumption and dissipation. Although higher power dissipation may be tolerable with some high-performance processors, it quickly leads to problems for portable machines. Assuming that the total gate-on-silicon surface area of an IC is of the order of 0.1 cm2, this would lead to 10 W static power consumption for an oxide thickness of 1.2 nm at 1 V supply.
Alternative high-κ dielectricsThe solution requires a thicker film with a higher dielectric constant. A desirable alternative gate insulator material would have a dielectric constant of about 15-40, leading to an increase in film thickness by a factor of 4-10 without changing the capacitance. The term equivalent oxide thickness (EOT) refers to the thickness of any dielectric scaled by the ratio of its dielectric constant to that of SiO2 (3.9). The use of such high-κ dielectrics would provide the EOTs required to maintain current drive, while keeping the tunneling current at an acceptably low level (table 2).
At first glance, this would seem to be a winning proposal, since a substantial reduction in the current should be possible by just increasing the layer thickness. However, there is another factor influencing the tunneling current - the barrier height between the electrode/silicon channel and the appropriate bands of the insulator. Therefore, not only is a material with a higher dielectric constant required, but this material must also have suitably large barrier heights, to keep the gate leakage currents within reasonable limits. Other basic limitations for high-κ substitutions include chemical and physical bonding constraints. Bonding at the Si-SiO2 (and also SiSi3N4) interface is isovalent, with bond charge exactly matching nuclear charge. Most high-κ materials are generally more ionic, and also more highly coordinated on average than SiO2. One would expect these dielectrics to form heterovalent interfaces with Si, with a mismatch between bond and nuclear charge. This mismatch can give rise to interfacial traps and/or fixed charges reducing carrier mobility.
Material selectionA systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon; (b) thermodynamic stability; (c) film morphology; (d) interface quality; (e) compatibility with the current or expected materials to be used in device processing; (f) process compatibility; and (g) reliability.
Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. The most common of these are the simple binary metal oxides such as Ta2O5, TiO2, ZrO2 and HfO2. Ferroelectric materials such as barium strontium titanate have also been suggested as gate dielectrics. Unfortunately, a number of these materials, specifically Ta2O5 and TiO2, are not stable on silicon, and even assuming that there is a material with a reasonably high-κ that reduces the leakage current for a given EOT, there is still the problem of integrating this material into device fabrication processes.
The easiest integration would involve direct substitution of the SiO2 in a given CMOS process with no further changes. Unfortunately, most of the materials studied are not sufficiently stable thermally. They can change phase (and therefore their material properties) at much lower temperatures than are needed for CMOS processing. The high-κ dielectric would be most likely deposited on a silicon channel; therefore it should not show any tendency to form silicides, silicates, silicon oxides, or mixtures of these during post-deposition annealing. In addition, chemical reactions of the metal oxide with capping poly-Si have been observed for most of the materials being studied. The aggressive scaling of FETs aggravates the problems of poly-Si gate depletion, high gate resistance, and dopant penetration from the highly-doped poly-Si gate into the channel region. As a result, there is immense interest in metal gate technology. At least one, if not two gate materials would have to be metals. Since most of the materials would not be compatible with the high temperatures required for most CMOS processes, the whole gate stack processing might have to be moved to the end of the device fabrication process instead of remaining at the beginning.
Aside from the issues related to the thermal stability of these high-κ materials, other processes including the chemical and reactive ion etching of these materials and new gate electrodes will also have to be developed. Moreover, introduction of gate dielectrics other than SiO2 requires that these be prepared by deposition, rather than conventional thermal growth processes. Therefore, the use of high-κ materials would require not only the discovery and development of a new material, but possibly a complete re-engineering of the CMOS manufacturing process.
The gate dielectric problemSiO2 has been used as the primary gate dielectric material in field-effect devices since the beginning, and the thickness of SiO2 films has decreased with each device generation. Table 1 shows the timeline for the anticipated future size reduction and the required oxide thickness. In a production environment it is very difficult to obtain oxides thinner than 8-10 Å as will be required in the next 5 years.
One of the fundamental limits to the scaling of the gate dielectric is the exponential increase in tunnel current with decreasing film thickness. For SiO2, at a gate bias of ~1 V, the leakage current changes from ~10-6 A/cm2 at ~3 nm to ~10 A/cm2 at ~1.5 nm - seven orders of magnitude in current for a thickness change of only a factor of 2. A high gate leakage current can conceivably alter device performance, to say nothing of the difficulties associated with power consumption and dissipation. Although higher power dissipation may be tolerable with some high-performance processors, it quickly leads to problems for portable machines. Assuming that the total gate-on-silicon surface area of an IC is of the order of 0.1 cm2, this would lead to 10 W static power consumption for an oxide thickness of 1.2 nm at 1 V supply.
Alternative high-κ dielectricsThe solution requires a thicker film with a higher dielectric constant. A desirable alternative gate insulator material would have a dielectric constant of about 15-40, leading to an increase in film thickness by a factor of 4-10 without changing the capacitance. The term equivalent oxide thickness (EOT) refers to the thickness of any dielectric scaled by the ratio of its dielectric constant to that of SiO2 (3.9). The use of such high-κ dielectrics would provide the EOTs required to maintain current drive, while keeping the tunneling current at an acceptably low level (table 2).
At first glance, this would seem to be a winning proposal, since a substantial reduction in the current should be possible by just increasing the layer thickness. However, there is another factor influencing the tunneling current - the barrier height between the electrode/silicon channel and the appropriate bands of the insulator. Therefore, not only is a material with a higher dielectric constant required, but this material must also have suitably large barrier heights, to keep the gate leakage currents within reasonable limits. Other basic limitations for high-κ substitutions include chemical and physical bonding constraints. Bonding at the Si-SiO2 (and also SiSi3N4) interface is isovalent, with bond charge exactly matching nuclear charge. Most high-κ materials are generally more ionic, and also more highly coordinated on average than SiO2. One would expect these dielectrics to form heterovalent interfaces with Si, with a mismatch between bond and nuclear charge. This mismatch can give rise to interfacial traps and/or fixed charges reducing carrier mobility.
Material selectionA systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon; (b) thermodynamic stability; (c) film morphology; (d) interface quality; (e) compatibility with the current or expected materials to be used in device processing; (f) process compatibility; and (g) reliability.
Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. The most common of these are the simple binary metal oxides such as Ta2O5, TiO2, ZrO2 and HfO2. Ferroelectric materials such as barium strontium titanate have also been suggested as gate dielectrics. Unfortunately, a number of these materials, specifically Ta2O5 and TiO2, are not stable on silicon, and even assuming that there is a material with a reasonably high-κ that reduces the leakage current for a given EOT, there is still the problem of integrating this material into device fabrication processes.
The easiest integration would involve direct substitution of the SiO2 in a given CMOS process with no further changes. Unfortunately, most of the materials studied are not sufficiently stable thermally. They can change phase (and therefore their material properties) at much lower temperatures than are needed for CMOS processing. The high-κ dielectric would be most likely deposited on a silicon channel; therefore it should not show any tendency to form silicides, silicates, silicon oxides, or mixtures of these during post-deposition annealing. In addition, chemical reactions of the metal oxide with capping poly-Si have been observed for most of the materials being studied. The aggressive scaling of FETs aggravates the problems of poly-Si gate depletion, high gate resistance, and dopant penetration from the highly-doped poly-Si gate into the channel region. As a result, there is immense interest in metal gate technology. At least one, if not two gate materials would have to be metals. Since most of the materials would not be compatible with the high temperatures required for most CMOS processes, the whole gate stack processing might have to be moved to the end of the device fabrication process instead of remaining at the beginning.
Aside from the issues related to the thermal stability of these high-κ materials, other processes including the chemical and reactive ion etching of these materials and new gate electrodes will also have to be developed. Moreover, introduction of gate dielectrics other than SiO2 requires that these be prepared by deposition, rather than conventional thermal growth processes. Therefore, the use of high-κ materials would require not only the discovery and development of a new material, but possibly a complete re-engineering of the CMOS manufacturing process.
