Applied and Soitec to develop GeOI wafers
The two companies will combine Soitec’s Smart Cut technology and engineered substrate expertise with the advanced epitaxial deposition capabilities of the Applied Centura RP Epi system to speed the development and production of these future generation substrates. The focus will be to develop germanium epitaxial layers that will be transferred using Soitec’s Smart Cut technology to build the GeOI wafers.
“Germanium compounds are expected to provide the foundation of many advanced materials in future chips, starting at the 45nm node,” said Randhir Thakur, VP and general manager of Applied Materials’ Front End Products group. “Working with Soitec, the leader in SOI (silicon-on-insulator) and other engineered substrates, we can exploit the unique capabilities of our epitaxial technology.
“By aligning our respective 45 nm technology roadmaps, we can accelerate our shared goal of developing cost-effective 300 mm GeOI manufacturing processes to enable the volume production of tomorrow’s GeOI-based chips.”
Germanium-based materials show great promise for future high-speed logic applications because of faster electron transport compared with silicon, potentially resulting in a 3-4x improvement in transistor switching speed. Because of bulk silicon’s scaling limitations at and beyond the 45 nm chip generation, many chipmakers are evaluating engineered GeOI-type substrates to enhance device performance.
