Euro team develops hafnium high-k process
Research at STMicroelectronics, in conjunction with CEA-Leti and Aixtron, has led to an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers.
Using an atomic vapor deposition process and Aixtron’s reactor technology, the team says it has produced HfO2/SiO/2/Si stacks with an equivalent oxide thickness of 1.15 nm, and leakage current densities of 0.068Acm-2 at 1.5V.
The process targets low-power applications at the 65nm and 45nm CMOS transistor technology nodes, and significantly reduces transistor leakage current by the deposition of ‘high-k’ gate-insulation material.
“These proof-of-concept results are a first for this process technology,” said Daniel Bensahel, project leader and front-end program director at the Franco-Italian semiconductor manufacturer STMicroelectronics.
The technology will assist with the demand for miniaturization of microelectronics, as described by Moore’s law, via the international technology roadmap for semiconductors.
CEA-Leti, based in Grenoble, France, is a microelectronics and microtechnologies research lab.
