Technical Insight
GaN transistors and power amplifiers close in on commercialization
With the cellular infrastructure industry promising to offer III-V device manufacturers the first substantial application market for GaN-based electronics, Ed Piner reports on the latest efforts to push commercialization of AlGaN/GaN HFET technology at Nitronex Corporation.
AlGaN/GaN heterostructure field-effect transistors (HFETs) significantly extend the design space of microwave power amplifiers due to their high breakdown field, high electron saturation velocity and high operating temperature. For example, AlGaN/GaN HFET structures can achieve gate-to-drain breakdown voltages of around 100 V/µm and maximum current densities exceeding 1 A/mm, resulting in power densities several times higher than commercially available devices.
At the product level, these superior attributes translate into higher operating voltages which simplify system design, result in smaller chips and packages, and enable higher device impedances that can extend the achievable bandwidths. Early-generation AlGaN/GaN HFET devices already show competitive performance compared with incumbent technologies, and further improvements are foreseen with more advanced device structures.
To be viable in commercial or military applications, operational performance must be complemented by adequate device stability and reliability. Most existing reliability studies on GaN focus on the stability of individual components, such as ohmic or Schottky contacts, and are typically limited to small sample sizes at the laboratory level. We have completed a comprehensive high-temperature operating life (HTOL) test that predicts excellent 20 year life stability.
GaN-on-siliconA patented technology known as SIGANTIC has been developed by Nitronex that allows growth of high-quality GaN-on-silicon substrates. Using this technology, along with our GaN wafer fabrication facility, a power transistor technology designed specifically for the output stage of third-generation wireless base stations has been developed and tested.
Following the success of solving the difficulties that the silicon substrate crystal structure and accompanying material properties posed for GaN growth, the benefits of the GaN-on-silicon platform technology are now being fully realized. First, the rapid scaling from 2 inch to 100 mm diameter wafers has been achieved, providing a means to reach the quantity, manufacturability and cost requirements of today s mature commercial semiconductor-processing fabs.
An equally significant achievement has been the development of a stable, uniform and repeatable device-fabrication process. This achievement was the result of the ability to run high volumes of GaN wafers and establish a manufacturing baseline through a processing fab employing standard 100 mm equipment, and exploiting the mature state of silicon processing for backside and packaging technologies. These silicon technologies include thinning, backside via, and Au-Si eutectic die attachment.
The economic advantage of silicon substrates has allowed this substantial volume of wafers to be produced during process development. During 2003, our 100 mm fabrication facility processed more than 1100 AlGaN/GaN HFET wafers, with a large percentage of these processed through assembly. A selection of packaged devices from each wafer is subjected to extensive DC and RF testing. With this data set, performance trends can be identified and correlations clearly established that would be lost to statistical variation in smaller sample sizes.
A significant level of engineering activity is constantly under way in order to meet performance and yield targets. A variety of methods is employed, including design of experiments, split lots, and physical simulation. Additionally, a percentage of the capacity is always dedicated to running lots of standardized process flow, referred to as baseline lots. All recipes, procedures and tests associated with these lots are maintained under revision control. The process delivers a constant standard of devices for product development, reliability studies and customer sampling. Baseline lots also serve to provide a relatively large body of data against which many experiments are assessed. Changes to the baseline are only adopted following the completion of a qualification event. A qualification event typically involves anywhere from 4 to 24 wafers, and includes data collection through packaged testing.
RF transistor performanceUsing a scalable transistor power cell, large gate periphery devices have been designed and fabricated. Typical device geometries range from 30 to 75 mm total gate peripheries fabricated on 1 x 6 mm die. With power densities of about 2 W/mm, these devices exhibit more than 60 W of total saturated continuous-wave (CW) output power with correspondingly high efficiency. The devices are optimized for operation at 2.14 GHz and are designed for good thermal dissipation, which is critical for high-power devices. Furthermore, these large single-chip devices can be combined in standard microwave packages to yield even higher total output power levels.
The performance requirements for the output power stage of third-generation wireless base stations are challenging for any device technology. The application requires that the devices are able to deliver an amplified signal with minimal signal distortion, while still operating at high efficiency and high output power levels. The choice of operating conditions for these devices is key to delivering the desired performance. We have determined that the optimal conditions for single-tone performance differ from those under W-CDMA modulation. The parameters that have a significant impact on the performance include the quiescent bias current, the source impedance and the load impedance. Transistors in this application are typically operated in a "backed-off" condition, with output power levels more than 6 dB below the full or saturated capability of the device. The peak output power for these devices needs to be in the range of 60-240 W, with a corresponding drain efficiency of 55% or higher, in order to be competitive.
The performance of a Nitronex device under CW RF drive with an unmodulated single-tone input at 2.14 GHz is shown in figure 1. The dual-chip AlGaN/GaN HFET-on-silicon device, mounted in a single-ended package, has a total gate periphery of 72 mm and a gate length of 0.7 mm. The operating condition for this device is a quiescent current (Idq) of 2 A and a drain voltage (Vds) of 28 V. The device demonstrates 16.3 dB of small signal gain, 62% drain efficiency, and a saturated output power of 138 W, a record output power for a GaN-on-silicon device at 28 V bias.
GaN device stabilityEach wafer from the baseline production process is sampled for wafer-acceptance testing. The standard procedure is to sample a minimum of five devices from each wafer. The devices are subjected to a 24 h HTOL burn-in test. The test is performed using a custom-built system capable of biasing up to 100 devices at a dissipated power level of 90 W each. The HTOL system uses liquid cooling to maintain a base-plate temperature of approximately 22ºC.
The burn-in test is intended to stabilize the device performance and to provide a first glimpse at the reliability behavior. The criteria for device failure during burn-in are either catastrophic (device burn-out) or a change in any parameter greater than ±15%, or ±0.5 dB. For our GaN devices, no burn-out while under bias has been observed.
Using the same set-up as described above, a 1500 h HTOL test has been performed on 45 devices with a 16 mm gate periphery. The samples were taken from five wafers representing three different process lots. One device from each wafer was used as a test control. The means for each parameter from the 24, 48, 168, 500, 1000 and 1500 h test down-points have been empirically fitted to log curves.
The results for drain-source saturation current (IDSS) are shown in figure 2. Each bar represents the entire data set with 100% of the devices surviving the HTOL test. The saturated current is stable, with a degradation of 6% over the duration of the test. Furthermore, when the 24 h burn-in effect is negated, the DC parameters tested are extrapolated to change less than 10% over 20 years.
The results for saturated output power (Psat) are shown in figure 3. Projecting the curves forward, we find that the Psat degradation is also stable, and is expected to change less than 1.0 dB from 24 h through 20 years.
Further testing has indicated that the infant mortality levels have remained consistently below 1%. Additionally, AlGaN/GaN HFET devices have passed a battery of additional reliability tests. These include temperature cycle (-65/150ºC over 250 cycles), autoclave (121ºC, 15 psi and 96 h), and electrostatic discharge testing at 500 and 1000 V.
Commercial applicationsOf immediate commercial interest, the emerging third-generation wireless cellular networks are designed to provide high-data-rate services beyond traditional voice. To support these higher data rates, third-generation air interfaces such as W-CDMA place severe constraints on the linearity of the power amplifier and associated power transistors. On the base station side, silicon lateral diffused metal oxide semiconductor (LDMOS) devices are the present technology leader, owing to their excellent price-to-performance ratio compared with other commercially available technologies such as GaAs HFETs and silicon bipolar junction transistors. Although LDMOS has supremacy, AlGaN/GaN HFETs are beginning to show their long-held research and development promise as contenders for high-power transistor applications.
Generally, SIGANTIC can be applied to both optoelectronic and microelectronic device structures. The fundamental properties of GaN offer much potential for high-power, high-frequency applications. GaN-on-silicon is able to meet the manufacturability and reliability requirements of today s more demanding applications. Equally important, the use of silicon substrates will ensure the economical viability of the technology. Given the high power densities and breakdown voltages achievable with this technology, it will prove enabling to many future applications.
At the product level, these superior attributes translate into higher operating voltages which simplify system design, result in smaller chips and packages, and enable higher device impedances that can extend the achievable bandwidths. Early-generation AlGaN/GaN HFET devices already show competitive performance compared with incumbent technologies, and further improvements are foreseen with more advanced device structures.
To be viable in commercial or military applications, operational performance must be complemented by adequate device stability and reliability. Most existing reliability studies on GaN focus on the stability of individual components, such as ohmic or Schottky contacts, and are typically limited to small sample sizes at the laboratory level. We have completed a comprehensive high-temperature operating life (HTOL) test that predicts excellent 20 year life stability.
GaN-on-siliconA patented technology known as SIGANTIC has been developed by Nitronex that allows growth of high-quality GaN-on-silicon substrates. Using this technology, along with our GaN wafer fabrication facility, a power transistor technology designed specifically for the output stage of third-generation wireless base stations has been developed and tested.
Following the success of solving the difficulties that the silicon substrate crystal structure and accompanying material properties posed for GaN growth, the benefits of the GaN-on-silicon platform technology are now being fully realized. First, the rapid scaling from 2 inch to 100 mm diameter wafers has been achieved, providing a means to reach the quantity, manufacturability and cost requirements of today s mature commercial semiconductor-processing fabs.
An equally significant achievement has been the development of a stable, uniform and repeatable device-fabrication process. This achievement was the result of the ability to run high volumes of GaN wafers and establish a manufacturing baseline through a processing fab employing standard 100 mm equipment, and exploiting the mature state of silicon processing for backside and packaging technologies. These silicon technologies include thinning, backside via, and Au-Si eutectic die attachment.
The economic advantage of silicon substrates has allowed this substantial volume of wafers to be produced during process development. During 2003, our 100 mm fabrication facility processed more than 1100 AlGaN/GaN HFET wafers, with a large percentage of these processed through assembly. A selection of packaged devices from each wafer is subjected to extensive DC and RF testing. With this data set, performance trends can be identified and correlations clearly established that would be lost to statistical variation in smaller sample sizes.
A significant level of engineering activity is constantly under way in order to meet performance and yield targets. A variety of methods is employed, including design of experiments, split lots, and physical simulation. Additionally, a percentage of the capacity is always dedicated to running lots of standardized process flow, referred to as baseline lots. All recipes, procedures and tests associated with these lots are maintained under revision control. The process delivers a constant standard of devices for product development, reliability studies and customer sampling. Baseline lots also serve to provide a relatively large body of data against which many experiments are assessed. Changes to the baseline are only adopted following the completion of a qualification event. A qualification event typically involves anywhere from 4 to 24 wafers, and includes data collection through packaged testing.
RF transistor performanceUsing a scalable transistor power cell, large gate periphery devices have been designed and fabricated. Typical device geometries range from 30 to 75 mm total gate peripheries fabricated on 1 x 6 mm die. With power densities of about 2 W/mm, these devices exhibit more than 60 W of total saturated continuous-wave (CW) output power with correspondingly high efficiency. The devices are optimized for operation at 2.14 GHz and are designed for good thermal dissipation, which is critical for high-power devices. Furthermore, these large single-chip devices can be combined in standard microwave packages to yield even higher total output power levels.
The performance requirements for the output power stage of third-generation wireless base stations are challenging for any device technology. The application requires that the devices are able to deliver an amplified signal with minimal signal distortion, while still operating at high efficiency and high output power levels. The choice of operating conditions for these devices is key to delivering the desired performance. We have determined that the optimal conditions for single-tone performance differ from those under W-CDMA modulation. The parameters that have a significant impact on the performance include the quiescent bias current, the source impedance and the load impedance. Transistors in this application are typically operated in a "backed-off" condition, with output power levels more than 6 dB below the full or saturated capability of the device. The peak output power for these devices needs to be in the range of 60-240 W, with a corresponding drain efficiency of 55% or higher, in order to be competitive.
The performance of a Nitronex device under CW RF drive with an unmodulated single-tone input at 2.14 GHz is shown in figure 1. The dual-chip AlGaN/GaN HFET-on-silicon device, mounted in a single-ended package, has a total gate periphery of 72 mm and a gate length of 0.7 mm. The operating condition for this device is a quiescent current (Idq) of 2 A and a drain voltage (Vds) of 28 V. The device demonstrates 16.3 dB of small signal gain, 62% drain efficiency, and a saturated output power of 138 W, a record output power for a GaN-on-silicon device at 28 V bias.
GaN device stabilityEach wafer from the baseline production process is sampled for wafer-acceptance testing. The standard procedure is to sample a minimum of five devices from each wafer. The devices are subjected to a 24 h HTOL burn-in test. The test is performed using a custom-built system capable of biasing up to 100 devices at a dissipated power level of 90 W each. The HTOL system uses liquid cooling to maintain a base-plate temperature of approximately 22ºC.
The burn-in test is intended to stabilize the device performance and to provide a first glimpse at the reliability behavior. The criteria for device failure during burn-in are either catastrophic (device burn-out) or a change in any parameter greater than ±15%, or ±0.5 dB. For our GaN devices, no burn-out while under bias has been observed.
Using the same set-up as described above, a 1500 h HTOL test has been performed on 45 devices with a 16 mm gate periphery. The samples were taken from five wafers representing three different process lots. One device from each wafer was used as a test control. The means for each parameter from the 24, 48, 168, 500, 1000 and 1500 h test down-points have been empirically fitted to log curves.
The results for drain-source saturation current (IDSS) are shown in figure 2. Each bar represents the entire data set with 100% of the devices surviving the HTOL test. The saturated current is stable, with a degradation of 6% over the duration of the test. Furthermore, when the 24 h burn-in effect is negated, the DC parameters tested are extrapolated to change less than 10% over 20 years.
The results for saturated output power (Psat) are shown in figure 3. Projecting the curves forward, we find that the Psat degradation is also stable, and is expected to change less than 1.0 dB from 24 h through 20 years.
Further testing has indicated that the infant mortality levels have remained consistently below 1%. Additionally, AlGaN/GaN HFET devices have passed a battery of additional reliability tests. These include temperature cycle (-65/150ºC over 250 cycles), autoclave (121ºC, 15 psi and 96 h), and electrostatic discharge testing at 500 and 1000 V.
Commercial applicationsOf immediate commercial interest, the emerging third-generation wireless cellular networks are designed to provide high-data-rate services beyond traditional voice. To support these higher data rates, third-generation air interfaces such as W-CDMA place severe constraints on the linearity of the power amplifier and associated power transistors. On the base station side, silicon lateral diffused metal oxide semiconductor (LDMOS) devices are the present technology leader, owing to their excellent price-to-performance ratio compared with other commercially available technologies such as GaAs HFETs and silicon bipolar junction transistors. Although LDMOS has supremacy, AlGaN/GaN HFETs are beginning to show their long-held research and development promise as contenders for high-power transistor applications.
Generally, SIGANTIC can be applied to both optoelectronic and microelectronic device structures. The fundamental properties of GaN offer much potential for high-power, high-frequency applications. GaN-on-silicon is able to meet the manufacturability and reliability requirements of today s more demanding applications. Equally important, the use of silicon substrates will ensure the economical viability of the technology. Given the high power densities and breakdown voltages achievable with this technology, it will prove enabling to many future applications.
