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SiC defects slashed with new growth scheme

A Japanese team may have opened the door to widespread commercial application of SiC devices through a new growth method that reduces substrate defects in the material by three orders of magnitude.

Widespread commercial application of SiC-based electronic devices appears to be much closer now that a Japanese team has made large-diameter SiC substrates with vastly reduced numbers of defects.

Writing in the prestigious scientific journal Nature (26th August issue, page 1009), Daisuke Nakamura and his colleagues at Toyota and DENSO Corporation say that they have rendered SiC substrates "virtually dislocation-free".

"We have succeeded in manufacturing a large-size substrate, which makes feasible commercial applications," said the team in its paper. "It will be possible in the near future to eliminate dislocations perfectly, and to enlarge the [substrate] diameter to several inches."

Until now, growth of SiC wafers has been plagued with large concentrations of defects. This has meant that only a very few commercial applications of the material, such as in Schottky diodes, have been possible so far.

Bipolar SiC devices have tended to suffer from a degradation in the material s electrical properties that appears to originate from in-plane dislocations.

Nakamura s team made the breakthrough by employing "repeated a-face growth" (RAF). Starting with a single SiC crystal grown on an a-face, and which consequently had a high density of dislocations, the team took a section of this crystal along its a-axis.

Then, they allowed the crystal to develop on its other a-face, before continuing with conventional c-face growth. It appears to be repetition of the a-face step that eliminates stacking faults and which suppresses dislocations.

In a 20 mm-diameter substrate grown with RAF, the average etch-pit density (EPD) was 75 cm-1, three orders of magnitude lower than conventional SiC substrates.

The result for micropipes was even better, which were completely eliminated in the RAF-grown wafers.

The team also made some PIN devices using the technique. According to Nakamura and colleagues, these were found to much more reliable than is normally the case.

With a view to making the technology suitable for commercial deployment, the team then set about increasing the crystal size to a much wider diameter. They made a 3-inch substrate, whose average EPD was two orders of magnitude lower than found in conventionally-grown material.

The growth technology may be used in other materials too, provided that the crystal structure is hexagonal.

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