RF applications beckon as strained silicon shapes up

With no alternative gate-dielectric materials ready to replace silicon dioxide, silicon chip manufacturers are increasingly turning away from scaling and towards the use of strained materials to boost transistor speed and maintain the march of Moore s Law.

As such, strained-silicon technology in its various forms is incorporated on the International Technology Roadmap for Semiconductors (ITRS). The ITRS emerging materials team defines three types of strained silicon: bulk strained silicon; strained silicon on insulator (s-SOI); and strained silicon on SiGe on insulator (SGOI).

The central fact driving the development of the technology is this: strained layers of silicon improve carrier mobility compared with standard relaxed silicon. This means that transistors can operate at a higher speed (see Further information).

Biaxial strain Bulk strained silicon has already found its way into high-end digital devices made by the likes of Intel, Texas Instruments and IBM. Having begun shipping SOI-based microprocessors in 2000, IBM is pushing a major research effort in the strained-silicon field. In US patent 6,649,492, awarded in November 2003, IBM describes a UHV-CVD method that can be used to manufacture strained-silicon devices. IBM distinguished engineer Gary Bronner told Compound Semiconductor that the company s research wing has demonstrated significant improvements in electron mobility by using biaxial strain.

"The advantages of increased electron and hole mobility through the use of strain are quite compelling," said Bronner. "Rather than wait for the technology that is required to make the s-SOI substrates mature, IBM has found other means to introduce strain in the channels of the SOI transistors during conventional processing."

According to Bronner, the basic idea is to deposit strained films and then transfer the stress from these deposited films onto the SOI substrate. IBM started doing this with its 90 nm SOI products that were launched in the first quarter of this year. "In our current 90 nm technology we believe we are seeing more than a 10% performance advantage from the use of strain," Bronner said.

Intel first revealed that it was using strained silicon in its 90 nm logic process back in 2002. At the International Electron Devices Meeting in December the following year, the world s biggest chip maker further expanded on the technology it had developed, which features 45 nm gate-length CMOS transistors.

Intel uses a selectively deposited SiGe source-drain structure to induce channel strain in PMOS devices (see figure 1). According to the company, this improves drive current by 25% relative to standard devices. Intel Senior Fellow Mark Bohr adds that incorporating a high-stress cap layer of Si3N4 material creates strain in NMOS devices, improving drive current by 10%. And the effect on cost is minimal - Bohr estimates that the double optimization only adds 2% to the process cost. Intel initially ramped up the strained-silicon process at its D1C fab in Oregon this year.

Despite these initial steps, the major impact of s-SOI technology is not expected to take off until at least 2007-2008. Said IBM s Bronner: "s-SOI is being actively explored for the 45 nm generation. It needs to meet aggressive goals in terms of starting wafer cost and defect density to ultimately make it into manufacturing. It also needs to show compelling advantages over other techniques for introducing strain into the silicon transistors."

So the use of s-SOI technology is not a foregone conclusion, according to Bronner. "The use of strain to boost transistor performance in silicon is inevitable. Whether s-SOI is used to introduce this strain or other techniques are adopted is still undecided."

Until recently, one of the major problems with s-SOI technology was the sheer number of defects and dislocations in s-SOI substrates. According to Soitec, the French company at the forefront of advanced silicon substrate development, the number of defects has now been reduced by a factor of 100 to 1000 compared with the previous industry standard.

Soitec says that, following a recent development project with ASM International of the Netherlands, it can now make s-SOI substrates of a quality similar to that of standard SOI and bulk silicon. Soitec has been sampling 200 mm s-SOI wafers for more than a year already, and plans to be the first company to offer 300 mm materials. It is in the process of upgrading its production line for sampling and pilot manufacturing.

Soitec sees s-SOI as a possible technology for the 45 nm silicon chip generation that is scheduled for implementation in 2007-2008, but ultimately it will depend on the demand from device manufacturers.

Soitec is not the only company looking to advance strained-silicon substrate technology. Silicon Genesis (SiGen) of the US recently developed its own wafer-level strained substrate. SiGen says that the key advantage of its substrates is that they feature uniaxial strain, where the strain is directed in a single axis across the wafer, rather than biaxial strain, which operates in both axes across the wafer surface.

According to SiGen, uniaxial strain is more effective than biaxial strain when it comes to enhancing the performance of PMOS transistors, particularly when a high effective electric field of around 1 MV/cm is applied. "Biaxial strain has been plagued with process integration issues such as high defect levels and germanium interdiffusion, but more importantly it is much less efficient at boosting PMOS transistor performance," said Scott Thompson, a former Intel Fellow and previously director of the company s strained-silicon program.

Until recently, says SiGen, uniaxial strain could only be induced locally, for example in the transistors made by Intel. The company s key breakthrough has been to achieve global uniaxial strain across a complete wafer, which should boost transistor performance further.

"Production costs are expected to be significantly lower than with biaxial technologies because [our process] avoids the costly steps of growing and relaxing thick SiGe layers," said François Henley, SiGen s CEO, of the technology, which could be implemented in both bulk silicon and s-SOI.

Suited to RF Although logic devices are the obvious focus for the likes of Intel and IBM, and they undoubtedly offer the bigger market potential, RF applications are also within the reach of s-SOI. Soitec has collaborated with ST Microelectronics and Renesas on this front. ST is actively developing RF devices based on standard SOI technology, and has demonstrated that SOI-CMOS coupled with a high-resistivity substrate is suitable for fully integrated microwave applications up to 5 GHz.

Strained-silicon specialist AmberWave Systems is a pioneer in the field, and has sampled its technology to around 15 device manufacturers. Chief technology officer Mayank Bulsara says that now the fundamental doubts about the technology have been overcome, the main issue that needs to be addressed is that of yield - a sure sign that the technology is moving towards commercial deployment.

AmberWave recently bagged $21 million in Series D financing and will use this to complete the commercialization of its bulk strained-silicon technology, although much of this cash will be spent on R&D. The company has also been busy assessing the potential of strained-silicon for RF applications. In a paper presented at the International SiGe Technology and Devices Meeting in May this year, AmberWave s researchers concluded that strained silicon has "excellent" suitability for analog and RF switching, and "good" prospects for RF low-noise amplifiers. And although there are question marks over its suitability for RF power amplifiers (mainly because of the adverse effect of self-heating), it seems clear to AmberWave that RF and analog functions suit the technology.

In the first demonstration of the RF and analog properties of a standard digital MOSFET process, AmberWave, Texas Instruments and International Sematech collaborated to make a direct comparison between strained bulk silicon and the standard material.

With a germanium composition of 20%, strained-silicon devices demonstrated an electron mobility enhancement of 90% at an effective field of 1 MV/cm. With a gate length of 0.15 µm they also showed an improved cut-off frequency (ft) of 44 GHz compared with the 34 GHz of standard material. "Strained-silicon CMOS has tremendous potential for RF and analog circuit applications," concluded the team.

Other recent developments in RF applications include a strained-silicon HFET operating in the microwave region. Researchers at DaimlerChrysler in Germany and Paris-Sud University in France have found that by replacing the thick relaxed buffers (that are traditionally used to study SiGe for microwave applications) with much thinner substrates, the RF and low-frequency noise characteristics can be "greatly improved".

Photonic future AmberWave s Bulsara can see yet another role for devices based on variants of SiGe, where high carrier mobility, light emission and detection, and light-routing capability are integrated on a single chip. "The SiGe alloy system is the key to integrating high-mobility transistors with optoelectronic interconnect technology economically," Bulsara said. In his opinion, now that strained-silicon transistors are being commercialized, the future will bring germanium-based photodetectors integrated with silicon. This technology was recently advanced by researchers at IBM (see Germanium-on-insulator detectors could crack interconnect bottleneck).

Bulsara even envisages a time when lasers can be manufactured on a silicon platform, making use of SiGe graded layer technology. "All photonic technologies on silicon using SiGe graded layers are an extension of the mobility-enhanced transistor technology that is being commercialized today," he said.

Further information

Creating the strain Layers of strained silicon, which have a carrier mobility that is higher than conventional silicon, incorporate germanium to generate the required tensile strain in the crystal lattice. Although crystalline germanium and silicon have the same lattice structure, the larger germanium atoms are spaced 4.2% further apart than silicon atoms. Alloys of SiGe have a lattice constant somewhere between that of the two pure crystals, whose exact value depends on the proportion of the two elements incorporated in the alloy.

Grown on top of a SiGe template, the atoms in a thin layer of pure silicon will attempt to align with the atoms below it and therefore be spaced further apart than normal - thus creating a "strained" layer as the silicon is stretched like a rubber membrane. However, fabricating a high-quality SiGe template presents its own difficulties, and switching from a pure silicon substrate to the alloy inevitably causes threading dislocations and other defects in the final structure.

According to Soitec, the way around this is to epitaxially grow a stack of layers on top of the silicon, beginning with a buffer layer where the proportion of germanium is graded from zero at the interface to up to 50% at the top. Another SiGe template layer is grown on top, with a lattice constant matched to the buffer below. This creates a fully relaxed template, with no strain, upon which a strained-silicon layer may be deposited optimally.

In strained-silicon-on-insulator (s-SOI) technology, the advantages of strained silicon are combined with the benefits of ultra-thin SOI layers, where a layer of insulation allows SOI-based chips to function at a much higher speed and lower power.