IBM's strained germanium is CMOS-compatible
IBM researchers claim to have made strained-germanium transistors using a technique compatible with conventional CMOS processing.
The PMOSFET devices, which were manufactured using two different methods, showed a three-fold improvement in drive current compared with standard silicon transistors.
Using either local thermal mixing (TM) or selective ultrahigh vacuum CVD processing, strained-germanium channels were realized on pre-patterned SiGe-on-insulator regions (see figures).
After forming the germanium layer, the IBM team, which is based at the company s T.J. Watson Research Center in New York, used a standard CMOS process to complete the devices.
According to IBM, the development, which will be detailed at next week s International Electron Devices Meeting (IEDM), demonstrates for the first time that strained-germanium devices can be manufactured using conventional IC fabrication techniques.
"IBM has demonstrated methods that can selectively place the strained germanium on the selected areas of a chip using a CMOS-compatible process," said the company in a statement.
As chip makers face an increasingly uphill struggle to keep pace with Moore s Law, the use of strain and alternative materials to conventional silicon in future ICs is becoming increasingly likely.
"System performance depends on chip performance, and that will increasingly depend on new materials and design techniques rather than simple scaling," said T.C. Chen, IBM s VP of Science and Technology.
"With this work we ve drawn on our experience [gained in] introducing technologies like SiGe, silicon-on-insulator and strained silicon."
IBM added that it believed the strained-germanium technology could feature in future chip generations with circuit sizes of 32 nm and smaller. According to current industry roadmaps, devices with these feature sizes are expected to emerge around the end of the decade.
The company also said that the manufacturing technology it has developed provides the device improvement without affecting other devices or circuits on the same chip. "This dramatically reduces the risk of introducing a new material," it claimed.
IBM s TM-grown devices may also help the development of an alternative dielectric material to SiO2. Some of the transistors fabricated featured a 3 nm HfO2 gate dielectric deposited using MOCVD. IBM said that the use of germanium-based devices provides an "easier path" towards the introduction of so-called high-k insulators.
