IBM and Intel make high-k gate breakthrough
Chip heavyweights Intel and IBM say that they have developed so-called "high-k" gate dielectrics that will ensure the continuation of Moore s Law using silicon-based transistors for much of the next decade.
The separate development efforts "“ both announced on January 27 "“ may appear to deliver a blow to proponents of III-V transistor technology that has been touted as a potential successor to silicon logic, although Intel s existing technology roadmap does not feature III-V materials until 2013 at the earliest.
Over decades of incremental improvements to CMOS processing, the limitations of the SiO2 gate dielectric layer have hung over the silicon industry as its single biggest technical challenge.
To improve transistor performance in the past, chip manufacturers have shrunk the thickness of the gate dielectric to as little as five atomic layers (1.2 nm). Although this has helped transistors reach very high speeds, the problem is that these very thin layers of SiO2 tend to leak a lot of current, resulting in energy waste and a build-up of heat.
The silicon industry has been working on high-k dielectric materials (i.e. materials that can hold a lot of electric charge without leaking) for a long time, but finding a complete solution to the leakage problem had proved elusive, and prompted many researchers to look to inherently faster III-V materials to produce speedier chips.
Now, though, Intel says that its combination of a high-k dielectric based on hafnium and a secret new metal gate material compatible with hafnium will cut source-drain leakage by more than five times, while improving the transistor drive current by more than 20 percent.
Intel founder Gordon Moore described the new approach, which is already being implemented in five products based on Intel s 45 nm transistors, as the "biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s".
IBM has come up with a slightly different solution to the leakage problem, but is also using a high-k metal gate. However, it says that it will only apply the new technology to its 45 nm chips some time in 2008.
"After more than ten years of effort, we now have a way forward," said T C Chen, VP of science and technology at IBM Research.
Freescale has been among the biggest supporters of III-V chips for logic, and last year it revealed details of an early-stage GaAs MOSFET (see related story). However, speaking at Compound Semiconductor magazine's Key Conference in November 2006, Freescale senior technical fellow Karl Johnson said, "If a high-k dielectric for silicon is developed, silicon trumps." That would now appear to be the case.
But some proponents of III-V MOSFET structures believe that the latest developments at Intel and IBM will help III-V devices penetrate new markets, by instigating greater convergence of the compound and silicon industries.
David Braddock, CEO of MBE specialist OSEMI and a long-time exponent of MOSFETs based on GaAs and GaN, said, "The watchword is convergence. High-k is at the center of this, and high-k GaN MOSFET technology will provide the extension of GaN s capability."
"High-k compound semiconductor MOSFETs will be able to leverage the millions of man years of silicon circuit designs," added Braddock. He believes that the successful implementation of high-k dielectrics at Intel is due to using vacuum techniques for molecular deposition, rather than relying on the wet oxidation approach that has failed in the past.
Outside of logic devices, there may also be some other applications where III-V MOSFET technology can prove useful, Johnson indicated.
For example, a III-V "LDMOS" approach could be employed in wireless infrastructure power amplifiers, where there are limits on the silicon LDMOS performance when it comes to producing high gain at frequencies of 5 GHz and above.