Glasgow team gets $7.7m to develop III-V logic
The UK s Engineering and Physical Sciences Research Council (EPSRC) has approved a £4.1 million ($7.7 million) grant under which five teams at the University of Glasgow will work on the development of logic transistors based on compound semiconductors.
Iain Thayne is the lead researcher of the three-year project, which will be hosted at Glasgow s Nanoelectronics Research Centre, and will officially begin on May 1, 2007.
Entitled "III-V MOSFETs for ultimate CMOS", it will focus on delivering prototype compound semiconductor transistor technology that could be scaled up for volume production in a silicon-type manufacturing environment.
Five teams from Glasgow s Department of Electronics and Electrical Engineering, and Department of Physics and Astronomy, will contribute to the project, which will focus on the following areas:• compound semiconductor growth techniques
• electrical, chemical and structural characterization of materials and transistors
• computer simulations of transistor designs
• development of III-V processing techniques that are compatible with existing silicon approaches
• building prototype transistors.
Facilities at the NRC that may be used in the project include MBE equipment for thin-film deposition, electron beam lithography, and reactive ion etching machines. The University of Surrey s Ion Beam Centre and the Daresbury Laboratory s SuperSTEM advanced microscopy facility will also take part.
While advances in CMOS processing continue to push the performance of silicon transistors beyond previous limits - witness the twin development of so-called high-k dielectrics by IBM and Intel recently - a fundamental technology roadblock still faces chip manufacturers.
Although that roadblock may not be reached for another decade, research teams are already looking at the new technologies that may take over from traditional CMOS. "We are developing device technologies for applications at and beyond the 22 nm technology generation, where currently there is no consensus among the industry about which will be the manufacturable solution with the necessary performance," Thayne told compoundsemiconductor.net.
Over the past three years, the Glasgow team has been working with leading US chip manufacturer Freescale Semiconductor on the development of GaAs-based structures for digital applications.
One of the key breakthroughs in that partnership has been the production of a gallium-based gate oxide suitable for use in such structures, a problem that had been a key stumbling block in the past.
"In the coming three years, we plan to move to higher-mobility materials to further increase the drive current to meet the targets of the 22 nm generation," Thayne added. "The most obvious migration will be to look at high-indium-concentration materials."
GaAs will remain the basic material system of choice, with the Glasgow teams investigating the potential of hetero-integration based on germanium-on-insulator (GeOI) substrates.
Thayne explained, "As GaAs and germanium are lattice-matched, GeOI is a route to co-integrating III-V functionality on a silicon platform."
The recent commercial development of high-k materials, coupled with projects like Glasgow s, suggests that silicon and compound semiconductor technology are headed on a convergent path when it comes to the digital technologies of the future.
"The III-V oxides we are using are inherently high-k and we [also] work with metal gates," said Thayne. "The long-term aim is to use the hyper-integration strategy to co-integrate III-V functionality on a silicon platform and in a silicon manufacturing environment."
Applications of this convergent device technology should stretch beyond the digital domain, believes Thayne: "Now that they have finally been proven viable, III-V MOSFETs will find applications in RF and mixed-signal applications, as well as digital logic."
"There are [also] likely to be various sensor applications that can exploit the combination of the direct bandgap and high electron mobility of compound semiconductors with a device quality oxide," he said, adding that the semiconductor community was only now starting to consider the full potential of a III-V oxide where the semiconductor surface is genuinely unpinned and the oxide/semiconductor interface is of device quality.
Thayne reckons that demonstrating a device-quality oxide that is also compatible with high-mobility materials incorporating a high indium concentration will be one of the toughest challenges of the new project.
Another major headache will be finding a way to form ultra-low-resistance source-drain contacts that are able to exploit the properties of the high mobility channel materials.