IBM threatens GaAs applications with 3-D SiGe
by Andy Extance
Information technology giant IBM is bringing “through-silicon-vias” (TSVs) and the “breakthrough chip-stacking” they allow into production to extend its silicon based systems capabilities beyond current expected limits.
TSVs allow a wide range of performance improvements, but IBM is clear in stating that the first applications will be in wireless communications chips for power amplification in wireless LAN and handsets, and that GaAs applications will be targeted.
The new chips are already running in IBM s manufacturing lines and the company intends to provide samples to customers in the second half of 2007, with full production at three plants in New York State and Vermont scheduled for 2008.
The concept allows chips to be stacked on top of one another, rather than sitting side by side.
This eliminates the need for long metal wires and shortens the distance that information needs to travel by 1000 times.
The technique that IBM uses, generating vias by etching through wafers and filling the resulting gaps with metal, can also create 100 times more pathways for information to travel down.
In wireless communications technology, the through silicon via replaces wire bonds that are less efficient at transferring signals off the chip.
IBM claims currently to be able to improve power efficiency for SiGe based wireless products by 40%, with the accompanying size and battery life advantages that this brings.
When asked about IBM s intentions for the new technology, Jim Dunn, senior manager, Analog & Mixed Signal Technology Development confirmed, “We will be applying it where GaAs is currently used. It could be applied to WiMAX at some point in the future.”
He told compoundsemiconductor.net that IBM is intending to both use the chips in its own designs and commercialize them for sale to other systems manufacturers.
Dunn indicated IBM had found a solution to generate these chips that could easily be applied to large-scale manufacturing.
“The key advance was the development of through wafer via technology that is compatible with standard high volume silicon manufacturing capability,” he explained.
“This allows us to combine improved electrical performance with traditional silicon economies of scale.”
Author
Andy Extance is a reporter at compoundsemiconductor.net.
