Agilent proves that defects kill HBTs
"In a fairly large circuit, a selectable divider with nearly 200 transistors, we noticed a 2% drift in supply current over a typical lifetime," explained Thomas Low, senior R&D engineer at Agilent s Santa Rosa site. "Initially, this power-supply drift seemed a trivial thing and it only happened on a small fraction of IC parts, maybe 1 in 50, so many of us would have preferred to ignore it. But one of our product engineers, Kevin Alt, decided to dig deeper and realized that the reason the supply current was drifting was that the current gains in random individual transistors in the current mirror circuit were dying." This scenario posed the obvious question: why are a very small proportion of the HBTs failing at an early stage, while the others are unaffected?
This is not just an academic question for Agilent because it manufactures electronic test instruments, such as oscilloscopes, sources, and network and spectrum analyzers, containing hundreds or even thousands of GaAs HBTs shared among many ICs. "If you randomly toss a small population of transistors into these circuits and say that these HBTs will have their current gains die in a short time, then that s a very bleak prediction," explained Low.
These concerns drove Agilent to try to understand the reason for the infant current-gain failure in a small proportion of HBTs. Its investigative team stripped down and examined HBTs that had failed with various techniques, such as scanning electron microscopy and transmission electron microscopy. The result of this failure analysis was null, according to Low. Researchers did manage to find some process-induced defects, which Low describes as "warts", on metal lines and in passivation dielectrics but there was no significant correlation of these defects with HBT failures.
However, success eventually followed by employing a highly parallel method for reliability testing that was developed by Low s colleague, Bob Yeats. The traditional reliability-testing method, high-temperature operating-life testing cannot detect infant failures because the sample size is too small, typically being limited to less than 100 HBTs. In contrast, Yeats technique can measure between 12,800 and 100,000 HBTs per wafer (see box "Parallel approach to HBT reliability testing"), which is a large enough sample size to detect the small infant-mortality rates associated with these devices.
Agilent s researchers discovered that the probability per HBT of infant failure (Pqf) is proportional to the etch pitch density (EPD) of the underlying GaAs substrate (see figure 1). In fact, these two quantities are related by the equation Pqf = Aeb × EPD, which implies that the size of the emitter area directly governs the likelihood of a HBT suffering from early current-gain failure. Put another way, this data suggests that any HBT emitter-base junction that is pierced by a threading dislocation from the substrate will fail by current gain far sooner than its dislocation-free companions.
The above equation produces a good line through the data, but the data points show significant scatter (see figure 1). "There are at least two components to the vertical scatter," explained Low. "One is the intermittent presence of additional defects, from the epi and/or process, that cause infant failures – which are mechanisms that are currently unidentified. Another component is sampling error. If you only detect five failed HBTs within the sample tested on a given wafer, then there is a square-root-of-five uncertainty in the actual HBT failure rate for that wafer." For a fixed sample size, this effect will produce more scatter in the data at low EPDs. According to Low, there is also a horizontal scatter, which results from uncertainty in the actual dislocation density, due to EPD counting errors. This scatter is larger at higher EPDs, where separation between etch pits becomes comparable to their size.
By fabricating reliability-test circuits on epi material grown on N+ GaAs substrates, Agilent confirmed its belief that dislocations are the primary cause of HBT infant failure. This type of substrate is not suitable for making working RF devices. However, it can be used for DC reliability tests, and it has a dislocation density that s much lower than even the very best semi-insulating substrates, with an EPD of less than 100 cm–2. "We tested 100,000 transistors per wafer on three of these N+ wafers and we saw a total of three HBTs fail," remarked Low. The conclusion was that the additional tenfold reduction in dislocation density produced a similar fall in the infant failure rate.
Agilent believes that any further reductions in HBT infant mortality will only come through additional improvements in substrate EPD. The company is already specifying that AXT s incoming substrates must have an EPD of less than 1,200 cm–2 and it hopes that its recent published findings will encourage GaAs substrate suppliers to develop even lower EPD substrates.
The high number of HBTs in each Agilent chip could fool HBT power-amplifier (PA) manufacturers into thinking that their products are immune to the EPD problem, but this would be a mistake. That s because it is the total emitter area that actually matters. At Compound Semiconductor we note that the emitter area for a typical cell-phone PA is even larger than Agilent s largest circuit so, at a given EPD, the predicted infant-failure rate of PA circuits is even worse. Simple calculations show that a typical GSM-output stage alone. which has a total emitter area of 4 × 10–5 cm–2, will have a probability of infant current-gain failure of 83% for a typical liquid-encapsulated Czochralski (LEC) substrate (EPD = 45,000 cm–2) and 15% for typical vertical-gradient freeze (VGF) substrate (EPD = 4000 cm–2). These are startling figures that could motivate many HBT cell-phone PA manufacturers, who consume a much larger volume of material than Agilent, to also beat the drum for lower EPD GaAs substrates.
The high failure rate also begs the question: why are so many handsets still working? The most likely answer is that the HBTs in the cell phone slowly degrade, rather than suddenly failing. If the output power from the PA continuously and linearly degrades over time, then the bias-control circuitry will adjust accordingly. Since the PA monitors the transmit power, the PA bias will increase. This reduces the battery lifetime, which is annoying to the user. However, it does not stop the handset from operating, at least not immediately.
Agilent has also tried to establish the nature of the infant failure of the HBT and to see whether it differs from the wear-out failure. Infrared images of the test chip allowed the failed HBT to be identified by its lack of electroluminescence (see figure 3). This failed transistor was interrogated with various DC tests. The I(V) characteristics were generally similar to those of HBTs that had failed by the more common wear-out mode, but there was a difference in the time dependence of the base current. "The non-dislocation-driven wear-out mode has a base current versus time that is constant for some long period, and then, bam, over 10 hours it increases radically," Low explained. "But with the dislocation-driven failure mode, the base current versus time is rock-solid linear. It linearly increases as long as you keep stressing it, even well into beta [current-gain] failure" said Low.
According to him, the gradual increase in base current versus time for infant failures has an important practical implication for circuit reliability. Circuits that can operate with low current gain, such as emitter-coupled logic ICs, will continue to function for significantly longer under a given bias stress than circuits that are more sensitive to the current gain, like certain amplifiers and other analog circuits.
Low believes that Agilent s research effort has been very thorough. "At this point we have only to specify and verify the lowest possible EPDs". However, he does not see this as a triumph but rather as a restriction. "The lowest substrate EPDs available to us today come from AXT and have a value of less than 1200 cm–2. These defects affect yield and restrict the maximum level of integration of our circuits." And the only way out of this predicament, says Low, is for substrate suppliers to develop GaAs material with much lower EPD than that available today.
