DARPA funding signals InP-on-CMOS ambition
by Andy Extance
The US Defense Advanced Research Projects Agency has chosen three partners to work with it on a revolutionary mixed signal electronics program called COmpound Semiconductor Materials On Silicon (COSMOS).
Malibu, California, research lab HRL has said it s been awarded $18.2 million to bring the benefits of semiconductor integration to militarily important applications using analog-digital conversion, such as communications, digital sound and image processing.
Raytheon Integrated Defense Systems, based in Andover, Massachusetts, will work towards the same goal from different a technical direction, as will Redondo Beach, California, headquartered Northrop Grumman Space Technology.
Talking to compoundsemiconductor.net, COSMOS program manager Mark Rosker said that the three companies had each secured funding “of the same order of magnitude”.
COSMOS will work towards producing a 16 bit analog-to-digital converter (ADC) capable of operating with a 500 MHz bandwidth and a power dissipation of less than 4W.
In order to reach this target, two intermediary goals have been set. In phase one, the teams will prove the effectiveness of each integration technology by making a standard differential amplifier containing two InP and three silicon transistors.
This first 18-month phase is followed by a second, 15-month phase that refines the technique by making “the world s best digital-to analog converter”, according to Rosker. The total award figure quoted by HRL and entry to the final, 15-month long, mixed-signal challenge relies on successfully completing each of these two initial phases.
“In phase three we really do the impossible. We try and make an ADC 50 times or so better than anything that s out there,” Rosker said.
Going to extremes
Rosker says that there are two extremes of approach to the integration that can be conceived, which are under trial in COSMOS.
“One case is ideal assembly, where you re independently developing each of the transistors. After you have produced them you combine them together using some kind of interconnect,” he explained.
“It s just that instead of these chips being millimeter sized, we're now talking about chiplets which are micron sized, that you have placed down on top of the processed silicon CMOS wafer.”
“The other extreme is the monolithic approach, and there you have to figure out how to grow compound semiconductors on top of the silicon CMOS. And that's tough. You need to have a relatively low temperature process because you're growing on top of a processed wafer.”
Northrop Grumman is taking the assembly approach while the Raytheon team is taking the monlithic one. HRL, however, is taking an intermediate approach which involves bonding a partially processed InP wafer to a silicon CMOS wafer before then completing the processing.
Author
Andy Extance is a reporter at compoundsemiconductor.net.
