IQE develops InP-on-silicon transistors
by Richard Stevenson in Albuquerque, New Mexico
A partnership between IQE Inc., Raytheon, and Eugene Fitzgerald s group at MIT has built InP-on-silicon HEMTs and HBTs using Soitec s germanium-on-insulator (GeOI) substrates.
“This could be a potentially crucial step towards monolithic integration of III-V devices onto CMOS silicon,” said IQE principal scientist Dmitri Lubyshev during his presentation at the North American MBE conference in Albuquerque.
According to him, large scale HEMTs fabricated on this foreign platform produce a current gain of 55 and a breakdown voltage of 5.0 V. This compares favourably to equivalent devices grown on InP that have values of 60 and 4.9 V, respectively.
Smaller-area devices have also been made and the frequency response of these transistors is under investigation.
Room-temperature Hall measurements on the HEMTs indicate that the material s mobility is also promising. The silicon-based devices have a mobility of 8300 cm2V-1s-1, compared to 10200 cm2V-1s-1 for those grown on InP.
Both types of transistor were grown by MBE on 100 mm GeOI-on-silicon from Soitec. These templates were off-cut by 6 degrees in the direction and feature 400 nm of SiO2 and 100 nm of germanium.
A 0.5 micron thick GaAs layer and a 1.1 micron InAlAs layer were deposited onto this template to allow the transistors to be grown on lattice-matched material.
Lubyshev explained that germanium out-diffusion into the GaAs layer that can lead to high unintentional doping was not present in IQE s material. Electromechanical capacitance measurements show minimal charge build-up at the GeOI/GaAs interface.
Meanwhile, X-ray diffraction measurements demonstrate the high crystal quality of the GaAs layer, which has a well-defined full-width half maximum of 36 arcsec.
Author
Richard Stevenson is features editor at Compound Semiconductor magazine.
