RFMD gives the BiFET a new twist

Handset manufacturers operate in a very competitive environment. Success hinges on the release of new models with ever more features, which must be crammed into sleeker designs catering for the latest fashions. In this sector innovation is paramount, alongside the sourcing of smaller components that offer more bang for your buck.

At RF Micro Devices (RFMD) we are addressing the handset manufacturers wish-list with a unique BiFET process technology that delivers a complex, yet highly integrated and compact front-end module (FEM). The mobile s component count can then be reduced without sacrificing the number of features, their quality or the battery life.

Handset designers prefer to use FEMs with control lines operating directly off the transceiver s lower voltages and currents. Our BiFET technology fulfills this and can integrate new DC circuits – including voltage regulators, analog bias control and low-leakage logic – directly into the FEM. This increases functionality, cuts the number of supporting external components on the phone s board and ultimately reduces this handset s bill of materials.

We are by no means the only BiFET developer. Approaches that integrate a PHEMT below the HBT have been pioneered by Anadigics, TriQuint and WIN Semiconductors, while Skyworks has merged a MESFET into the HBT emitter layers. But in every case, the addition of a second device to the existing HBT process makes manufacturing more expensive and complex.

We minimize this extra complexity in the most cost-effective way with our unique BiFET process. Our advantage stems from the way that we integrate a junction FET (JFET) into the emitter layers of the HBT s epistructure. The JFET acts as a voltage variable resistor (VVR) and we often describe the device by this name because it reflects the application.

An overriding goal has dominated our BiFET development – reducing the additional process steps and changes required to add a FET to the existing InGaP/GaAs HBT epitaxial structure to ensure that our BiFETs manufacturing costs are only slightly higher than the traditional HBT-only process.

Our BiFET s epitaxial structure contains just two more layers than our HBT-only process – an InGaP etch stop and GaAs channel – and both are inserted between the cap and the InGaP emitter (figure 1). This epitaxial design has already been tried by researchers at the University of Illinois at Urbana-Champaign, but they restricted their studies to HBT devices. In that case the new design had no detrimental impact on transistor performance.

The VVR is notably different from other FETs that feature in BiFET technologies. There is no gate metal over the channel region, and a p-n heterojunction controls conduction between source and drain regions. The VVR s back-gate contact metal comes from the HBT base metal.

We isolate the source and drain with a wet recess etch to the InGaP etch-stop layer, and no gate metal deposition steps are needed for device fabrication. Identical metal layers provide contacts to the HBT emitter mesa and the source and drain contacts. The only additions to our InGaP HBT manufacturing process are another mask layer and one etch step.

Our tests show that no detrimental effects on BiFET HBT performance have resulted from the incorporation of the VVR. Gummel plots reveal that the BiFETs current gain, Β, matches that of the standalone device until the HBTs deliver a high collector current. Plots of the HBT collector current as a function of collector-emitter voltage are very similar for both processes, and small signal results show little difference between cut-off frequency and maximum oscillation frequency. However, the BiFET HBT has a lower emitter-base capacitance and the two additional epilayers produce an expected increase in emitter resistance, which is double that of the standalone HBT.

Of course, the ultimate test for any device is the performance that it delivers in its intended application. We ve checked this out by comparing the performance of WCDMA power amplifiers incorporating HBTs from our standalone process and the new BiFET process. We intentionally avoided taking advantage of any of the new VVR devices and retained the original InGaP/GaAs HBT process layout to carry out this evaluation. Keeping with this philosophy, the parts from the new and original processes were built to be as consistent as possible.

Performance was unaffected, according to measurements taken over temperature, bias condition, power level and Vcc (the DC voltage applied to the collector of multiple HBTs in a circuit). Encouragingly, characteristics such as power-added efficiency, adjacent channel power and gain were all within the part-to-part variation of the HBT-only process.

Our VVR s current-voltage characteristics are shown in figure 2. We have found that 0.7 µA/mm flows in the VVR when it is in its off state. When the drain-source voltage hits 4 V, leakage current must be kept low to avoid undesirable currents in the bias circuit. The current can be minimized by fine-tuning the manufacturing process and epitaxial structure.

High-yield manufacturing processes must account for and manage variation in VVR device performance and its effect on the circuit. Our BiFET design is notable for its absence of a gate metal above the channel, which creates a VVR device performance that strongly depends on epilayer thicknesses and doping concentrations. Our engineers are driving down these variations as the process matures and will monitor the changes in VVR that are caused by fluctuations in epilayer thickness and doping across the wafer and between runs.

We have also modeled device behavior (see box "Modeling the VVR transistor") to understand how our VVR behaves and how it can be integrated into more-complex circuits before production.

The WCDMA FEMs that we have developed will offer great value to our customers thanks to the incorporation of internal voltage regulators made from BiFETs. Ideally, internal voltage regulator circuits should deliver a constant voltage over all conditions, including variations in battery output, operating environment and load. BiFET-based internal regulators are configured in a different way, however, and must balance trade-offs to deliver a constant voltage over a limited range of conditions.

We are aware that some of our VVR device characteristics are not ideal. The VVR s low transconductance and drain cut-off current, and its "scalability" with gate width, mean that the easiest way to improve circuit performance is to place larger VVRs where more current is required. However, this goes against the trend of greater miniaturization.

Internal voltage regulator output is strongly influenced by the VVR s threshold voltage. Variations in this voltage can be minimized by summing two outputs: the regulated voltage and another output that is inversely proportional to the threshold voltage. A near constant regulated voltage results, which tracks the threshold voltage.

Internal voltage regulator circuits developed with our BiFET process exploit the VVR s ability to deliver a constant current at a fixed gate-source voltage across a wide range of drain-source voltages (figure 2a). Regulators can then be created to feed multiple circuits requiring a fixed voltage thanks to the HBT s ability to mirror currents.

Our BiFET process also enables logic with low-leakage currents – it is possible to create a low-leakage inverter with a combination of HBT and VVR devices. Our inverter s load has to be large enough to ensure a sufficiently low leakage current for the FEM (typically less than 10 µA), but high enough to drive the circuit.

It is possible to extend this concept and build AND, NAND, OR and NOR gates. In addition, FEMs with a digitally enabled internal regulator can be realized by uniting the building blocks of logic with a regulator (figure 3). Our BiFET can clearly deliver many desirable technologies while simplifying design, reducing the size of the circuits and cutting the total bill of materials.

Future goals include the exploration of new ways to exploit the inherent benefits of our unique BiFET technology and our approaches to drive the process to even higher yields. Ultimately, this should be good news for handset manufacturers.

Further reading
M Fresina et al. 1996 Electron Device Lett. 17 555.
T Henderson et al. 2007 CS MANTECH 247.
C K Lin et al. 2007 CS MANTECH 251.
A G Metzgar et al. 2006 CSIC 175.
B Moser et al. 2008 CS MANTECH 273.
M Shokrani et al. 2006 CS MANTECH 153.
P Zampardi et al. 2005 CS-MAX 32.   

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