IBM claims shortest gate length III-V MOSFETs
Computing giant IBM has made InGaAs MOSFETs that come closest to matching the dimensions of cutting-edge silicon logic devices of any fabricated to date.
A team from the company s New York T.J Watson Research Center describes 160 nm gate length transistors in the January 2009 issue of IEEE Electron Device Letters.
“In order to evaluate III-V logic it s critical to produce MOSFETs with gate length comparable to the state-of-the-art silicon devices,” explained Yanning Sun, a member of the IBM team.
At the same time the researchers tackled surface states, a key performance-limiting issue for III-V MOSFETS, by passivating the devices with amorphous silicon.
“Effective channel mobility in a MOSFET can be greatly degraded if the interface state density is high,” Sun told compoundsemiconductor.net. “The α-Si passivation effectively reduces the interface state density by successfully removing the III-V native oxides.”
Without using its passivation technique the team s longer-channel 5 µm gate length devices reached 1280 cm2/Vs peak effective carrier mobility. When the approach was exploited it enhanced this to 3810 cm2/Vs, determined at a carrier density of 1.8 x 1012 cm-2, a figure that Sun says is “among the best”.
“III-V MOSFETs effective channel mobility needs to be sufficiently higher than that in silicon devices in order to be considered for logic application,” she explained.
“However, the high mobility extracted from long-channel devices can not necessarily be preserved in the short-channel devices. Therefore, it s very important to demonstrate high mobility and high current in scaled III-V MOSFETs.”
Although carrier mobility was not determined for IBM s 160 nm gate length device, a related property - virtual source velocity - was up to 1.7 times higher than silicon MOSFETs. The InGaAs transistor operated with a drain current of 825 µA/µm.
Sun says that the short-channel devices had not been produced previously because fabrication processes are complicated and lengthy, currently requiring electron beam lithography.
The MOSFETs buried gate was made from a high-κ dielectric material, with a large gate overlap region due to the use of a non-self-aligned process. For CMOS applications, a self-aligned process is required and Sun points out that the IBM team has already demonstrated such a scheme for its InGaAs MOSFETs.
She also says that the team is now working on the high-κ gate and α-Si deposition processes to further improve the interface with the III-V layers.
